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Fix spacing issues. 

This patch removes space before a tab and space or tab before end
of line.
This commit is contained in:
Cary R 2010-09-14 16:10:41 -07:00 committed by Stephen Williams
parent 5ae3e48cdb
commit dd4fb9b4ef
49 changed files with 517 additions and 520 deletions
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126
examples/des.v
View File

@ -162,11 +162,11 @@ end
endmodule endmodule
module des(pt, key, ct, clk); module des(pt, key, ct, clk);
input [1:64] pt; input [1:64] pt;
input [1:64] key; input [1:64] key;
output [1:64] ct; output [1:64] ct;
input clk; input clk;
wire [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x; wire [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
wire [1:32] l0x,l1x,l2x,l3x,l4x,l5x,l6x,l7x,l8x,l9x,l10x,l11x,l12x,l13x,l14x,l15x,l16x; wire [1:32] l0x,l1x,l2x,l3x,l4x,l5x,l6x,l7x,l8x,l9x,l10x,l11x,l12x,l13x,l14x,l15x,l16x;
wire [1:32] r0x,r1x,r2x,r3x,r4x,r5x,r6x,r7x,r8x,r9x,r10x,r11x,r12x,r13x,r14x,r15x,r16x; wire [1:32] r0x,r1x,r2x,r3x,r4x,r5x,r6x,r7x,r8x,r9x,r10x,r11x,r12x,r13x,r14x,r15x,r16x;
@ -194,9 +194,9 @@ endmodule
module pc1(key, c0x, d0x); module pc1(key, c0x, d0x);
input [1:64] key; input [1:64] key;
output [1:28] c0x, d0x; output [1:28] c0x, d0x;
wire [1:56] XX; wire [1:56] XX;
assign XX[1]=key[57]; assign XX[2]=key[49]; assign XX[3]=key[41]; assign XX[4]=key[33]; assign XX[5]=key[25]; assign XX[6]=key[17]; assign XX[7]=key[9]; assign XX[1]=key[57]; assign XX[2]=key[49]; assign XX[3]=key[41]; assign XX[4]=key[33]; assign XX[5]=key[25]; assign XX[6]=key[17]; assign XX[7]=key[9];
assign XX[8]=key[1]; assign XX[9]=key[58]; assign XX[10]=key[50]; assign XX[11]=key[42]; assign XX[12]=key[34]; assign XX[13]=key[26]; assign XX[14]=key[18]; assign XX[8]=key[1]; assign XX[9]=key[58]; assign XX[10]=key[50]; assign XX[11]=key[42]; assign XX[12]=key[34]; assign XX[13]=key[26]; assign XX[14]=key[18];
@ -213,9 +213,9 @@ endmodule
module pc2(c,d,k); module pc2(c,d,k);
input [1:28] c,d; input [1:28] c,d;
output [1:48] k; output [1:48] k;
wire [1:56] YY; wire [1:56] YY;
assign YY[1:28]=c; assign YY[29:56]=d; assign YY[1:28]=c; assign YY[29:56]=d;
@ -231,7 +231,7 @@ endmodule
module rol1(o, i); module rol1(o, i);
output [1:28] o; output [1:28] o;
input [1:28] i; input [1:28] i;
assign o={i[2:28],i[1]}; assign o={i[2:28],i[1]};
@ -240,7 +240,7 @@ endmodule
module rol2(o, i); module rol2(o, i);
output [1:28] o; output [1:28] o;
input [1:28] i; input [1:28] i;
assign o={i[3:28],i[1:2]}; assign o={i[3:28],i[1:2]};
@ -248,10 +248,10 @@ endmodule
module keysched(key,k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x); module keysched(key,k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x);
input [1:64] key; input [1:64] key;
output [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x; output [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
wire [1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x; wire [1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x;
wire [1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x; wire [1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x;
pc1 pc1(key, c0x, d0x); pc1 pc1(key, c0x, d0x);
@ -294,10 +294,10 @@ endmodule
module s1(clk, b, so); module s1(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -370,10 +370,10 @@ endmodule
module s2(clk, b, so); module s2(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -446,10 +446,10 @@ endmodule
module s3(clk, b, so); module s3(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -522,10 +522,10 @@ endmodule
module s4(clk, b, so); module s4(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -598,10 +598,10 @@ endmodule
module s5(clk, b, so); module s5(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -674,10 +674,10 @@ endmodule
module s6(clk, b, so); module s6(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -750,10 +750,10 @@ endmodule
module s7(clk, b, so); module s7(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -826,10 +826,10 @@ endmodule
module s8(clk, b, so); module s8(clk, b, so);
input clk; input clk;
input [1:6] b; input [1:6] b;
output [1:4] so; output [1:4] so;
reg [1:4] so; reg [1:4] so;
always @(posedge clk) always @(posedge clk)
casex(b) casex(b)
@ -902,8 +902,8 @@ endmodule
module ip(pt, l0x, r0x); module ip(pt, l0x, r0x);
input [1:64] pt; input [1:64] pt;
output [1:32] l0x, r0x; output [1:32] l0x, r0x;
assign l0x[1]=pt[58]; assign l0x[2]=pt[50]; assign l0x[3]=pt[42]; assign l0x[4]=pt[34]; assign l0x[1]=pt[58]; assign l0x[2]=pt[50]; assign l0x[3]=pt[42]; assign l0x[4]=pt[34];
assign l0x[5]=pt[26]; assign l0x[6]=pt[18]; assign l0x[7]=pt[10]; assign l0x[8]=pt[2]; assign l0x[5]=pt[26]; assign l0x[6]=pt[18]; assign l0x[7]=pt[10]; assign l0x[8]=pt[2];
@ -941,10 +941,10 @@ endmodule
module desxor1(e,b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x,k); module desxor1(e,b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x,k);
input [1:48] e; input [1:48] e;
output [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x; output [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x;
input [1:48] k; input [1:48] k;
wire [1:48] XX; wire [1:48] XX;
assign XX = k ^ e; assign XX = k ^ e;
assign b1x = XX[1:6]; assign b1x = XX[1:6];
@ -960,9 +960,9 @@ endmodule
module pp(so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x,ppo); module pp(so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x,ppo);
input [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x; input [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x;
output [1:32] ppo; output [1:32] ppo;
wire [1:32] XX; wire [1:32] XX;
assign XX[1:4]=so1x; assign XX[5:8]=so2x; assign XX[9:12]=so3x; assign XX[13:16]=so4x; assign XX[1:4]=so1x; assign XX[5:8]=so2x; assign XX[9:12]=so3x; assign XX[13:16]=so4x;
assign XX[17:20]=so5x; assign XX[21:24]=so6x; assign XX[25:28]=so7x; assign XX[29:32]=so8x; assign XX[17:20]=so5x; assign XX[21:24]=so6x; assign XX[25:28]=so7x; assign XX[29:32]=so8x;
@ -980,8 +980,8 @@ endmodule
module desxor2(d,l,q); module desxor2(d,l,q);
input [1:32] d,l; input [1:32] d,l;
output [1:32] q; output [1:32] q;
assign q = d ^ l; assign q = d ^ l;
@ -994,10 +994,10 @@ input [1:32] li, ri;
input [1:48] k; input [1:48] k;
output [1:32] lo, ro; output [1:32] lo, ro;
wire [1:48] e; wire [1:48] e;
wire [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x; wire [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x;
wire [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x; wire [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x;
wire [1:32] ppo; wire [1:32] ppo;
xp xp(ri, e); xp xp(ri, e);
desxor1 desxor1(e, b1x, b2x, b3x, b4x, b5x, b6x, b7x, b8x, k); desxor1 desxor1(e, b1x, b2x, b3x, b4x, b5x, b6x, b7x, b8x, k);
@ -1018,7 +1018,7 @@ endmodule
module fp(l,r,ct); module fp(l,r,ct);
input [1:32] l,r; input [1:32] l,r;
output [1:64] ct; output [1:64] ct;
assign ct[1]=r[8]; assign ct[2]=l[8]; assign ct[3]=r[16]; assign ct[4]=l[16]; assign ct[5]=r[24]; assign ct[6]=l[24]; assign ct[7]=r[32]; assign ct[8]=l[32]; assign ct[1]=r[8]; assign ct[2]=l[8]; assign ct[3]=r[16]; assign ct[4]=l[16]; assign ct[5]=r[24]; assign ct[6]=l[24]; assign ct[7]=r[32]; assign ct[8]=l[32];

8
examples/pal_reg.v
View File

@ -55,12 +55,12 @@
module register (out, val, clk, oe); module register (out, val, clk, oe);
output [7:0] out; output [7:0] out;
input [7:0] val; input [7:0] val;
input clk, oe; input clk, oe;
reg [7:0] Q; reg [7:0] Q;
wire [7:0] out; wire [7:0] out;
bufif0 drv[7:0](out, Q, oe); bufif0 drv[7:0](out, Q, oe);

4
examples/sqrt-virtex.v
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@ -252,7 +252,7 @@ endmodule // sqrt32
module main; module main;
reg [31:0] x; reg [31:0] x;
reg clk, reset; reg clk, reset;
wire [15:0] y; wire [15:0] y;
wire rdy; wire rdy;
@ -354,7 +354,7 @@ module chip_root(clk, rdy, reset, x, y);
input [31:0] x; input [31:0] x;
output [15:0] y; output [15:0] y;
wire clk_int; wire clk_int;
(* cellref="BUFG:O,I" *) (* cellref="BUFG:O,I" *)
buf gbuf (clk_int, clk); buf gbuf (clk_int, clk);

4
net_scope.cc
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@ -251,14 +251,14 @@ void NetScope::print_type(ostream&stream) const
break; break;
case FORK_JOIN: case FORK_JOIN:
stream << "parallel block"; stream << "parallel block";
break; break;
case FUNC: case FUNC:
stream << "function"; stream << "function";
break; break;
case MODULE: case MODULE:
stream << "module <" << (module_name_ ? module_name_.str() : "") stream << "module <" << (module_name_ ? module_name_.str() : "")
<< "> instance"; << "> instance";
break; break;
case TASK: case TASK:
stream << "task"; stream << "task";
break; break;

2
symbol_search.cc
View File

@ -61,7 +61,7 @@ NetScope*symbol_search(const LineInfo*li, Design*des, NetScope*scope,
cerr << li->get_fileline() << ": error: Hierarchical " cerr << li->get_fileline() << ": error: Hierarchical "
"reference to automatically allocated item " "reference to automatically allocated item "
"`" << key << "' in path `" << path << "'" << endl; "`" << key << "' in path `" << path << "'" << endl;
des->errors += 1; des->errors += 1;
} }
hier_path = true; hier_path = true;

1
tgt-vhdl/vhdl_target.h
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@ -35,4 +35,3 @@ void prune_wait_for_0(stmt_container *container);
void require_support_function(support_function_t f); void require_support_function(support_function_t f);
#endif /* #ifndef INC_VHDL_TARGET_H */ #endif /* #ifndef INC_VHDL_TARGET_H */

2
tgt-vvp/eval_expr.c
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@ -2589,7 +2589,7 @@ static struct vector_info draw_select_unsized_literal(ivl_expr_t expr,
/* If we have an undefined index then just produce a 'bx result. */ /* If we have an undefined index then just produce a 'bx result. */
fprintf(vvp_out, " %%jmp/1 T_%d.%d, 4;\n", thread_count, lab_x); fprintf(vvp_out, " %%jmp/1 T_%d.%d, 4;\n", thread_count, lab_x);
/* If the subv result is a magic constant, then make a copy in /* If the subv result is a magic constant, then make a copy in
writable vector space and work from there instead. */ writable vector space and work from there instead. */
if (subv.base < 4) { if (subv.base < 4) {
res.base = allocate_vector(subv.wid); res.base = allocate_vector(subv.wid);

3
vvp/array.cc
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@ -769,7 +769,7 @@ static unsigned vpi_array_is_real(vvp_array_t arr)
assert(arr->array_count > 0); assert(arr->array_count > 0);
struct __vpiRealVar*rsig = vpip_realvar_from_handle(arr->nets[0]); struct __vpiRealVar*rsig = vpip_realvar_from_handle(arr->nets[0]);
if (rsig) { if (rsig) {
struct __vpiSignal*vsig = vpip_signal_from_handle(arr->nets[0]); struct __vpiSignal*vsig = vpip_signal_from_handle(arr->nets[0]);
assert(vsig == 0); assert(vsig == 0);
return 1U; return 1U;
} }
@ -1503,7 +1503,6 @@ void vpip_array_word_change(struct __vpiCallback*cb, vpiHandle obj)
void vpip_array_change(struct __vpiCallback*cb, vpiHandle obj) void vpip_array_change(struct __vpiCallback*cb, vpiHandle obj)
{ {
struct __vpiArray*arr = ARRAY_HANDLE(obj); struct __vpiArray*arr = ARRAY_HANDLE(obj);
cb->extra_data = -1; // This is a callback for every element. cb->extra_data = -1; // This is a callback for every element.
cb->next = arr->vpi_callbacks; cb->next = arr->vpi_callbacks;

2
vvp/examples/vector.vvp
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@ -2,7 +2,7 @@
main .scope module, "main"; main .scope module, "main";
T0 %vpi_call 0 0 "$display", "Display the number: %b", 5'b0zx1; T0 %vpi_call 0 0 "$display", "Display the number: %b", 5'b0zx1;
%end; %end;
.thread T0; .thread T0;
:file_names 2; :file_names 2;

4
vvp/schedule.h
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@ -65,9 +65,9 @@ extern void schedule_assign_array_word(vvp_array_t mem,
* Create an event to propagate the output of a net. * Create an event to propagate the output of a net.
*/ */
extern void schedule_propagate_plucked_vector(vvp_net_t*ptr, extern void schedule_propagate_plucked_vector(vvp_net_t*ptr,
vvp_time64_t delay, vvp_time64_t delay,
const vvp_vector4_t&val, const vvp_vector4_t&val,
unsigned adr, unsigned wid); unsigned adr, unsigned wid);
/* /*
* This is very similar to schedule_assign_vector, but generates an * This is very similar to schedule_assign_vector, but generates an

4
vvp/vvp_net.cc
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@ -1870,8 +1870,8 @@ void vvp_vector4array_aa::reset_instance(vvp_context_t context)
for (unsigned idx = 0 ; idx < words_ ; idx += 1) { for (unsigned idx = 0 ; idx < words_ ; idx += 1) {
if (cell->abits_ptr_) { if (cell->abits_ptr_) {
for (unsigned n = 0 ; n < cnt ; n += 1) { for (unsigned n = 0 ; n < cnt ; n += 1) {
cell->abits_ptr_[n] = vvp_vector4_t::WORD_X_ABITS; cell->abits_ptr_[n] = vvp_vector4_t::WORD_X_ABITS;
cell->bbits_ptr_[n] = vvp_vector4_t::WORD_X_BBITS; cell->bbits_ptr_[n] = vvp_vector4_t::WORD_X_BBITS;
} }
} }
cell++; cell++;

1
vvp/vvp_net.h
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@ -65,7 +65,6 @@ typedef void*vvp_context_item_t;
inline vvp_context_t vvp_allocate_context(unsigned nitem) inline vvp_context_t vvp_allocate_context(unsigned nitem)
{ {
return (vvp_context_t)malloc((2 + nitem) * sizeof(void*)); return (vvp_context_t)malloc((2 + nitem) * sizeof(void*));
} }