diff --git a/driver/globals.h b/driver/globals.h index 22be7a12e..810787f93 100644 --- a/driver/globals.h +++ b/driver/globals.h @@ -40,10 +40,10 @@ extern void process_include_dir(const char*name); /* Add a new -D define. */ extern void process_define(const char*name); - + /* Add a new parameter definition */ extern void process_parameter(const char*name); - + /* Set the default timescale for the simulator. */ extern void process_timescale(const char*ts_string); diff --git a/driver/iverilog.man.in b/driver/iverilog.man.in index a42a89b23..2cb0bc488 100644 --- a/driver/iverilog.man.in +++ b/driver/iverilog.man.in @@ -64,7 +64,7 @@ Verilog source for use by other compilers. .B -g1995\fI|\fP-g2001\fI|\fP-g2001-noconfig\fI|\fP-g2005\fI|\fP-g2009 Select the Verilog language \fIgeneration\fP to support in the compiler. This selects between \fIIEEE1364\-1995\fP, -\fIIEEE1364\-2001\fP, \fIIEEE1364\-2005\fP, or \fIIEEE1800-2009\fP. +\fIIEEE1364\-2001\fP, \fIIEEE1364\-2005\fP, or \fIIEEE1800-2009\fP. Normally, Icarus Verilog defaults to the latest known generation of the language. This flag is most useful to restrict the language to a set supported by tools of specific generations, for compatibility with diff --git a/elab_net.cc b/elab_net.cc index 6cccd5205..06ef24b51 100644 --- a/elab_net.cc +++ b/elab_net.cc @@ -497,7 +497,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope, /* The array has a part/bit select at the end. */ if (name_tail.index.size() > sig->array_dimensions()) { if (sig->get_scalar()) { - cerr << get_fileline() << ": error: " + cerr << get_fileline() << ": error: " << "can not select part of "; if (sig->data_type() == IVL_VT_REAL) cerr << "real"; else cerr << "scalar"; @@ -512,7 +512,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope, return 0; if (lidx_tmp < 0) { - cerr << get_fileline() << ": sorry: part selects " + cerr << get_fileline() << ": sorry: part selects " "straddling the start of signal (" << path_ << ") are not currently supported." << endl; des->errors += 1; @@ -523,7 +523,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope, } } else if (!name_tail.index.empty()) { if (sig->get_scalar()) { - cerr << get_fileline() << ": error: " + cerr << get_fileline() << ": error: " << "can not select part of "; if (sig->data_type() == IVL_VT_REAL) cerr << "real: "; else cerr << "scalar: "; @@ -537,7 +537,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope, return 0; if (lidx_tmp < 0) { - cerr << get_fileline() << ": sorry: part selects " + cerr << get_fileline() << ": sorry: part selects " "straddling the start of signal (" << path_ << ") are not currently supported." << endl; des->errors += 1; diff --git a/elaborate.cc b/elaborate.cc index a53d46733..70fe2a0b5 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -1422,7 +1422,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const des->errors += 1; continue; } - + // We do not support real inout ports at all. if (!prts.empty() && (prts[0]->data_type() == IVL_VT_REAL )) { cerr << pins[idx]->get_fileline() << ": error: " diff --git a/examples/des.v b/examples/des.v index a0eeff187..59cd0d370 100644 --- a/examples/des.v +++ b/examples/des.v @@ -162,11 +162,11 @@ end endmodule module des(pt, key, ct, clk); -input [1:64] pt; -input [1:64] key; -output [1:64] ct; -input clk; -wire [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x; +input [1:64] pt; +input [1:64] key; +output [1:64] ct; +input clk; +wire [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x; wire [1:32] l0x,l1x,l2x,l3x,l4x,l5x,l6x,l7x,l8x,l9x,l10x,l11x,l12x,l13x,l14x,l15x,l16x; wire [1:32] r0x,r1x,r2x,r3x,r4x,r5x,r6x,r7x,r8x,r9x,r10x,r11x,r12x,r13x,r14x,r15x,r16x; @@ -194,9 +194,9 @@ endmodule module pc1(key, c0x, d0x); -input [1:64] key; -output [1:28] c0x, d0x; -wire [1:56] XX; +input [1:64] key; +output [1:28] c0x, d0x; +wire [1:56] XX; assign XX[1]=key[57]; assign XX[2]=key[49]; assign XX[3]=key[41]; assign XX[4]=key[33]; assign XX[5]=key[25]; assign XX[6]=key[17]; assign XX[7]=key[9]; assign XX[8]=key[1]; assign XX[9]=key[58]; assign XX[10]=key[50]; assign XX[11]=key[42]; assign XX[12]=key[34]; assign XX[13]=key[26]; assign XX[14]=key[18]; @@ -213,9 +213,9 @@ endmodule module pc2(c,d,k); -input [1:28] c,d; -output [1:48] k; -wire [1:56] YY; +input [1:28] c,d; +output [1:48] k; +wire [1:56] YY; assign YY[1:28]=c; assign YY[29:56]=d; @@ -231,7 +231,7 @@ endmodule module rol1(o, i); -output [1:28] o; +output [1:28] o; input [1:28] i; assign o={i[2:28],i[1]}; @@ -240,7 +240,7 @@ endmodule module rol2(o, i); -output [1:28] o; +output [1:28] o; input [1:28] i; assign o={i[3:28],i[1:2]}; @@ -248,10 +248,10 @@ endmodule module keysched(key,k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x); -input [1:64] key; -output [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x; -wire [1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x; -wire [1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x; +input [1:64] key; +output [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x; +wire [1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x; +wire [1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x; pc1 pc1(key, c0x, d0x); @@ -294,10 +294,10 @@ endmodule module s1(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -370,10 +370,10 @@ endmodule module s2(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -446,10 +446,10 @@ endmodule module s3(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -522,10 +522,10 @@ endmodule module s4(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -598,10 +598,10 @@ endmodule module s5(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -674,10 +674,10 @@ endmodule module s6(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -750,10 +750,10 @@ endmodule module s7(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -826,10 +826,10 @@ endmodule module s8(clk, b, so); -input clk; -input [1:6] b; -output [1:4] so; -reg [1:4] so; +input clk; +input [1:6] b; +output [1:4] so; +reg [1:4] so; always @(posedge clk) casex(b) @@ -902,8 +902,8 @@ endmodule module ip(pt, l0x, r0x); -input [1:64] pt; -output [1:32] l0x, r0x; +input [1:64] pt; +output [1:32] l0x, r0x; assign l0x[1]=pt[58]; assign l0x[2]=pt[50]; assign l0x[3]=pt[42]; assign l0x[4]=pt[34]; assign l0x[5]=pt[26]; assign l0x[6]=pt[18]; assign l0x[7]=pt[10]; assign l0x[8]=pt[2]; @@ -941,10 +941,10 @@ endmodule module desxor1(e,b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x,k); -input [1:48] e; -output [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x; -input [1:48] k; -wire [1:48] XX; +input [1:48] e; +output [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x; +input [1:48] k; +wire [1:48] XX; assign XX = k ^ e; assign b1x = XX[1:6]; @@ -960,9 +960,9 @@ endmodule module pp(so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x,ppo); -input [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x; -output [1:32] ppo; -wire [1:32] XX; +input [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x; +output [1:32] ppo; +wire [1:32] XX; assign XX[1:4]=so1x; assign XX[5:8]=so2x; assign XX[9:12]=so3x; assign XX[13:16]=so4x; assign XX[17:20]=so5x; assign XX[21:24]=so6x; assign XX[25:28]=so7x; assign XX[29:32]=so8x; @@ -980,8 +980,8 @@ endmodule module desxor2(d,l,q); -input [1:32] d,l; -output [1:32] q; +input [1:32] d,l; +output [1:32] q; assign q = d ^ l; @@ -994,10 +994,10 @@ input [1:32] li, ri; input [1:48] k; output [1:32] lo, ro; -wire [1:48] e; +wire [1:48] e; wire [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x; wire [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x; -wire [1:32] ppo; +wire [1:32] ppo; xp xp(ri, e); desxor1 desxor1(e, b1x, b2x, b3x, b4x, b5x, b6x, b7x, b8x, k); @@ -1018,7 +1018,7 @@ endmodule module fp(l,r,ct); -input [1:32] l,r; +input [1:32] l,r; output [1:64] ct; assign ct[1]=r[8]; assign ct[2]=l[8]; assign ct[3]=r[16]; assign ct[4]=l[16]; assign ct[5]=r[24]; assign ct[6]=l[24]; assign ct[7]=r[32]; assign ct[8]=l[32]; diff --git a/examples/pal_reg.v b/examples/pal_reg.v index f959a6e1b..2207c88a1 100644 --- a/examples/pal_reg.v +++ b/examples/pal_reg.v @@ -55,12 +55,12 @@ module register (out, val, clk, oe); output [7:0] out; - input [7:0] val; - input clk, oe; + input [7:0] val; + input clk, oe; - reg [7:0] Q; + reg [7:0] Q; - wire [7:0] out; + wire [7:0] out; bufif0 drv[7:0](out, Q, oe); diff --git a/examples/sqrt-virtex.v b/examples/sqrt-virtex.v index bc95d4939..ad532eab3 100644 --- a/examples/sqrt-virtex.v +++ b/examples/sqrt-virtex.v @@ -252,7 +252,7 @@ endmodule // sqrt32 module main; reg [31:0] x; - reg clk, reset; + reg clk, reset; wire [15:0] y; wire rdy; @@ -354,7 +354,7 @@ module chip_root(clk, rdy, reset, x, y); input [31:0] x; output [15:0] y; - wire clk_int; + wire clk_int; (* cellref="BUFG:O,I" *) buf gbuf (clk_int, clk); diff --git a/expr_synth.cc b/expr_synth.cc index e58c2b30d..c279364ae 100644 --- a/expr_synth.cc +++ b/expr_synth.cc @@ -1328,7 +1328,7 @@ static NetEvWait* make_func_trigger(Design*des, NetScope*scope, NetExpr*root) delete nset; return trigger; -} +} NetNet* NetESFunc::synthesize(Design*des, NetScope*scope, NetExpr*root) { diff --git a/ivlpp/lexor.lex b/ivlpp/lexor.lex index b63fa377d..4f3577e89 100644 --- a/ivlpp/lexor.lex +++ b/ivlpp/lexor.lex @@ -1394,19 +1394,19 @@ static void do_expand(int use_args) str_buf[idx+1] = '0'; str_buf[idx+2] = '4'; str_buf[idx+3] = '2'; - idx += 4; - continue; + idx += 4; + continue; } if (*cp == '\\') { str_buf[idx] = '\\'; str_buf[idx+1] = '1'; str_buf[idx+2] = '3'; str_buf[idx+3] = '4'; - idx += 4; - continue; + idx += 4; + continue; } str_buf[idx] = *cp; - idx += 1; + idx += 1; } str_buf[idx] = 0; idx += 1; diff --git a/main.cc b/main.cc index 51cccfb1d..1370d2cb6 100644 --- a/main.cc +++ b/main.cc @@ -872,7 +872,7 @@ int main(int argc, char*argv[]) if (gn_cadence_types_flag) lexor_keyword_mask |= GN_KEYWORDS_ICARUS; - + if (gn_verilog_ams_flag) lexor_keyword_mask |= GN_KEYWORDS_VAMS_2_3; diff --git a/mingw.txt b/mingw.txt index c8a2ee063..af1c61489 100644 --- a/mingw.txt +++ b/mingw.txt @@ -84,7 +84,7 @@ Download the msys-1.x.x.exe and msysdtc-1.x.x.exe binaries. These are self-installing packages. Install msys first, and then msysDTC. Most likely, you want to install them in c:/msys. (The msysDTK is installed in the same location, as it is an add-on.) - + This install should be easy and reliable. The installation will leave an "msys" icon on your desktop and in the diff --git a/net_link.cc b/net_link.cc index 2bf71302c..e53f9da6a 100644 --- a/net_link.cc +++ b/net_link.cc @@ -382,7 +382,7 @@ void Nexus::unlink(Link*that) } // If the link I'm removing was a driver for this nexus, then - // cancel my guess of the driven value. + // cancel my guess of the driven value. if (that->get_dir() != Link::INPUT) driven_ = NO_GUESS; diff --git a/net_scope.cc b/net_scope.cc index c9760cd0c..ae84b6e39 100644 --- a/net_scope.cc +++ b/net_scope.cc @@ -251,14 +251,14 @@ void NetScope::print_type(ostream&stream) const break; case FORK_JOIN: stream << "parallel block"; - break; + break; case FUNC: stream << "function"; break; case MODULE: stream << "module <" << (module_name_ ? module_name_.str() : "") << "> instance"; - break; + break; case TASK: stream << "task"; break; diff --git a/parse.y b/parse.y index a9a5bfc3f..fe87b00e7 100644 --- a/parse.y +++ b/parse.y @@ -2052,7 +2052,7 @@ local_timeunit_prec_decl module : attribute_list_opt module_start IDENTIFIER { pform_startmodule($3, @2.text, @2.first_line, $1); } module_parameter_port_list_opt - module_port_list_opt + module_port_list_opt module_attribute_foreign ';' { pform_module_set_ports($6); } local_timeunit_prec_decl_opt diff --git a/pform.cc b/pform.cc index 973f52c70..230843bd2 100644 --- a/pform.cc +++ b/pform.cc @@ -62,7 +62,7 @@ void parm_to_defparam_list(const string¶m) key = strdup(param.substr(0, off).c_str()); value = strdup(param.substr(off+1).c_str()); } - + // Resolve hierarchical name for defparam. Remember // to deal with bit select for generate scopes. Bit // select expression should be constant interger. @@ -109,7 +109,7 @@ void parm_to_defparam_list(const string¶m) ptr = strchr(nkey, '.'); } name.push_back(name_component_t(lex_strings.make(nkey))); - + // Resolve value to PExpr class. Should support all kind of constant // format including based number, dec number, real number and string. if (*value == '"') { // string type @@ -127,13 +127,13 @@ void parm_to_defparam_list(const string¶m) cerr << ": error: missing close quote of string for defparam: " << name << endl; else if (*(buf_ptr+1) != 0) { // '"' appears within string with no escape cerr << buf_ptr << endl; - cerr << ": error: \'\"\' appears within string value for defparam: " << name + cerr << ": error: \'\"\' appears within string value for defparam: " << name << ". Ignore characters after \'\"\'" << endl; } - + *buf_ptr = '\0'; buf_ptr = buf+1; - // Remember to use 'new' to allocate string for PEString + // Remember to use 'new' to allocate string for PEString // because 'delete' is used by its destructor. char *nchar = strcpy(new char [strlen(buf_ptr)+1], buf_ptr); PExpr* ndec = new PEString(nchar); @@ -165,17 +165,17 @@ void parm_to_defparam_list(const string¶m) free(value); return; } - + // BASED_NUMBER with size, something like - scope.parameter=2'b11 if (num != value) { *num = 0; verinum *siz = make_unsized_dec(value); val = pform_verinum_with_size(siz, val, "", 0); } - + PExpr* ndec = new PENumber(val); Module::user_defparms.push_back( make_pair(name, ndec) ); - + } else { // REALTIME, something like - scope.parameter=1.22 or scope.parameter=1e2 @@ -799,7 +799,7 @@ void pform_endmodule(const char*name, bool inside_celldefine, tp_local_flag = false; } -static void pform_add_genvar(const struct vlltype&li, const perm_string&name, +static void pform_add_genvar(const struct vlltype&li, const perm_string&name, map&genvars) { LineInfo*lni = new LineInfo(); diff --git a/pform.h b/pform.h index 4d611ad8d..ea50b318a 100644 --- a/pform.h +++ b/pform.h @@ -418,7 +418,7 @@ extern PExpr* pform_make_branch_probe_expression(const struct vlltype&loc, extern PExpr* pform_make_branch_probe_expression(const struct vlltype&loc, char*name, char*branch); -/* +/* * Parse configuration file with format =, where key * is the hierarchical name of a valid parameter name and value * is the value user wants to assign to. The value should be constant. diff --git a/symbol_search.cc b/symbol_search.cc index f6ed3f527..8b8cadbfa 100644 --- a/symbol_search.cc +++ b/symbol_search.cc @@ -61,7 +61,7 @@ NetScope*symbol_search(const LineInfo*li, Design*des, NetScope*scope, cerr << li->get_fileline() << ": error: Hierarchical " "reference to automatically allocated item " "`" << key << "' in path `" << path << "'" << endl; - des->errors += 1; + des->errors += 1; } hier_path = true; diff --git a/tgt-vhdl/Makefile.in b/tgt-vhdl/Makefile.in index 533013cc9..ea04ee9a1 100644 --- a/tgt-vhdl/Makefile.in +++ b/tgt-vhdl/Makefile.in @@ -72,7 +72,7 @@ stamp-vhdl_config-h: $(srcdir)/vhdl_config.h.in ../config.status vhdl_config.h: stamp-vhdl_config-h clean: - rm -rf $(O) dep vhdl.tgt + rm -rf $(O) dep vhdl.tgt distclean: clean rm -f Makefile config.log diff --git a/tgt-vhdl/cast.cc b/tgt-vhdl/cast.cc index 9f54270a1..07540f71d 100644 --- a/tgt-vhdl/cast.cc +++ b/tgt-vhdl/cast.cc @@ -39,7 +39,7 @@ vhdl_expr *vhdl_expr::cast(const vhdl_type *to) // we can't generate any type conversion code if (NULL == type_) return this; - + if (to->get_name() == type_->get_name()) { if (to->get_width() == type_->get_width()) return this; // Identical @@ -79,7 +79,7 @@ vhdl_expr *vhdl_expr::to_vector(vhdl_type_name_t name, int w) vhdl_bit_spec_expr *bs = new vhdl_bit_spec_expr(new vhdl_type(name, w - 1, 0), others); bs->add_bit(0, this); - + return bs; } else { @@ -89,11 +89,11 @@ vhdl_expr *vhdl_expr::to_vector(vhdl_type_name_t name, int w) vhdl_type *t = new vhdl_type(name, w - 1, 0); vhdl_fcall *conv = new vhdl_fcall(t->get_string().c_str(), t); conv->add_expr(this); - + if (w != type_->get_width()) return conv->resize(w); else - return conv; + return conv; } } @@ -110,9 +110,9 @@ vhdl_expr *vhdl_expr::to_integer() } else conv = new vhdl_fcall("To_Integer", vhdl_type::integer()); - + conv->add_expr(this); - + return conv; } @@ -130,7 +130,7 @@ vhdl_expr *vhdl_expr::to_boolean() else if (type_->get_name() == VHDL_TYPE_UNSIGNED) { // Need to use a support function for this conversion require_support_function(SF_UNSIGNED_TO_BOOLEAN); - + vhdl_fcall *conv = new vhdl_fcall(support_function::function_name(SF_UNSIGNED_TO_BOOLEAN), vhdl_type::boolean()); @@ -139,7 +139,7 @@ vhdl_expr *vhdl_expr::to_boolean() } else if (type_->get_name() == VHDL_TYPE_SIGNED) { require_support_function(SF_SIGNED_TO_BOOLEAN); - + vhdl_fcall *conv = new vhdl_fcall(support_function::function_name(SF_SIGNED_TO_BOOLEAN), vhdl_type::boolean()); @@ -157,12 +157,12 @@ vhdl_expr *vhdl_expr::to_std_logic() { if (type_->get_name() == VHDL_TYPE_BOOLEAN) { require_support_function(SF_BOOLEAN_TO_LOGIC); - + vhdl_fcall *ah = new vhdl_fcall(support_function::function_name(SF_BOOLEAN_TO_LOGIC), vhdl_type::std_logic()); ah->add_expr(this); - + return ah; } else if (type_->get_name() == VHDL_TYPE_SIGNED) { @@ -196,7 +196,7 @@ vhdl_expr *vhdl_expr::to_std_ulogic() f->add_expr(this); return f; } - else + else assert(false); } @@ -219,11 +219,11 @@ vhdl_expr *vhdl_expr::resize(int newwidth) vhdl_binop_expr* concat = new vhdl_binop_expr(zeros, VHDL_BINOP_CONCAT, this, vhdl_type::nunsigned(newwidth)); - return concat; + return concat; } else return this; // Doesn't make sense to resize non-vector type - + vhdl_fcall *resizef = new vhdl_fcall("Resize", rtype); resizef->add_expr(this); resizef->add_expr(new vhdl_const_int(newwidth)); @@ -267,10 +267,10 @@ vhdl_expr *vhdl_const_bits::to_std_logic() // VHDL won't let us cast directly between a vector and // a scalar type // But we don't need to here as we have the bits available - + // Take the least significant bit char lsb = value_[0]; - + return new vhdl_const_bit(lsb); } @@ -280,14 +280,14 @@ char vhdl_const_bits::sign_bit() const } vhdl_expr *vhdl_const_bits::to_vector(vhdl_type_name_t name, int w) -{ +{ if (name == VHDL_TYPE_STD_LOGIC_VECTOR) { // Don't need to do anything return this; } else if (name == VHDL_TYPE_SIGNED || name == VHDL_TYPE_UNSIGNED) { // Extend with sign bit - value_.resize(w, sign_bit()); + value_.resize(w, sign_bit()); return this; } assert(false); @@ -304,8 +304,8 @@ vhdl_expr *vhdl_const_bits::resize(int w) // Rather than generating a call to Resize, when can just sign-extend // the bits here. As well as looking better, this avoids any ambiguity // between which of the signed/unsigned versions of Resize to use. - - value_.resize(w, sign_bit()); + + value_.resize(w, sign_bit()); return this; } diff --git a/tgt-vhdl/display.cc b/tgt-vhdl/display.cc index 75eca6110..1f95365ec 100644 --- a/tgt-vhdl/display.cc +++ b/tgt-vhdl/display.cc @@ -48,16 +48,16 @@ static void display_write(stmt_container *container, vhdl_expr *expr) // supported by std.textio std::string name(expr->get_type()->get_string()); name += "'Image"; - + vhdl_fcall *cast = new vhdl_fcall(name.c_str(), vhdl_type::string()); cast->add_expr(expr); - + write->add_expr(cast); } - else + else write->add_expr(expr); - + container->add_stmt(write); } @@ -125,7 +125,7 @@ int draw_stask_display(vhdl_procedural *proc, stmt_container *container, line_var->set_comment("For generating $display output"); proc->get_scope()->add_decl(line_var); } - + // Write the data into the line int count = ivl_stmt_parm_count(stmt), i = 0; while (i < count) { @@ -137,7 +137,7 @@ int draw_stask_display(vhdl_procedural *proc, stmt_container *container, display_write(container, new vhdl_const_string(" ")); continue; } - + if (ivl_expr_type(net) == IVL_EX_STRING) { ostringstream ss; for (const char *p = ivl_expr_string(net); *p; p++) { @@ -154,7 +154,7 @@ int draw_stask_display(vhdl_procedural *proc, stmt_container *container, } else if (*p == '%' && *(++p) != '%') { flush_string(ss, container); - + // Skip over width for now while (isdigit(*p)) ++p; @@ -167,11 +167,11 @@ int draw_stask_display(vhdl_procedural *proc, stmt_container *container, assert(i < count); ivl_expr_t netp = ivl_stmt_parm(stmt, i++); assert(netp); - + vhdl_expr *base = translate_expr(netp); if (NULL == base) return 1; - + display_write(container, base); } } @@ -181,20 +181,20 @@ int draw_stask_display(vhdl_procedural *proc, stmt_container *container, } // Call Write on any non-empty string data left in the buffer - if (!ss.str().empty()) + if (!ss.str().empty()) display_write(container, new vhdl_const_string(ss.str().c_str())); } else { vhdl_expr *base = translate_expr(net); - if (NULL == base) + if (NULL == base) return 1; - + display_write(container, base); } } if (newline) display_line(container); - + return 0; } diff --git a/tgt-vhdl/expr.cc b/tgt-vhdl/expr.cc index 78ce66882..11dd41683 100644 --- a/tgt-vhdl/expr.cc +++ b/tgt-vhdl/expr.cc @@ -35,7 +35,7 @@ static vhdl_expr *change_signedness(vhdl_expr *e, bool issigned) int msb = e->get_type()->get_msb(); int lsb = e->get_type()->get_lsb(); vhdl_type u(issigned ? VHDL_TYPE_SIGNED : VHDL_TYPE_UNSIGNED, msb, lsb); - + return e->cast(&u); } @@ -44,9 +44,9 @@ static vhdl_expr *change_signedness(vhdl_expr *e, bool issigned) * same signedness as the Verilog expression vl_e. */ static vhdl_expr *correct_signedness(vhdl_expr *vhd_e, ivl_expr_t vl_e) -{ +{ bool should_be_signed = ivl_expr_signed(vl_e) != 0; - + if (vhd_e->get_type()->get_name() == VHDL_TYPE_UNSIGNED && should_be_signed) { //operand->print(); @@ -69,7 +69,7 @@ static vhdl_expr *correct_signedness(vhdl_expr *vhd_e, ivl_expr_t vl_e) * Convert a constant Verilog string to a constant VHDL string. */ static vhdl_expr *translate_string(ivl_expr_t e) -{ +{ // TODO: May need to inspect or escape parts of this const char *str = ivl_expr_string(e); return new vhdl_const_string(str); @@ -82,12 +82,12 @@ static vhdl_expr *translate_string(ivl_expr_t e) static vhdl_var_ref *translate_signal(ivl_expr_t e) { ivl_signal_t sig = ivl_expr_signal(e); - + const vhdl_scope *scope = find_scope_for_signal(sig); assert(scope); const char *renamed = get_renamed_signal(sig).c_str(); - + vhdl_decl *decl = scope->get_decl(renamed); assert(decl); @@ -102,7 +102,7 @@ static vhdl_var_ref *translate_signal(ivl_expr_t e) vhdl_var_ref *ref = new vhdl_var_ref(renamed, new vhdl_type(*decl->get_type())); - + ivl_expr_t off; if (ivl_signal_array_count(sig) > 0 && (off = ivl_expr_oper1(e))) { // Select from an array @@ -152,7 +152,7 @@ static vhdl_expr *translate_reduction(support_function_t f, bool neg, vhdl_fcall *fcall = new vhdl_fcall(support_function::function_name(f), vhdl_type::std_logic()); - + vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR); fcall->add_expr(operand->cast(&std_logic_vector)); @@ -173,7 +173,7 @@ static vhdl_expr *translate_unary(ivl_expr_t e) return NULL; operand = correct_signedness(operand, e); - + char opcode = ivl_expr_opcode(e); switch (opcode) { case '!': @@ -234,7 +234,7 @@ static vhdl_expr *translate_relation(vhdl_expr *lhs, vhdl_expr *rhs, // Generate any necessary casts // Arbitrarily, the RHS is casted to the type of the LHS vhdl_expr *r_cast = rhs->cast(lhs->get_type()); - + return new vhdl_binop_expr(lhs, op, r_cast, vhdl_type::boolean()); } @@ -311,7 +311,7 @@ static vhdl_expr *translate_binary(ivl_expr_t e) vhdl_expr *lhs = translate_expr(ivl_expr_oper1(e)); if (NULL == lhs) return NULL; - + vhdl_expr *rhs = translate_expr(ivl_expr_oper2(e)); if (NULL == rhs) return NULL; @@ -319,7 +319,7 @@ static vhdl_expr *translate_binary(ivl_expr_t e) int lwidth = lhs->get_type()->get_width(); int rwidth = rhs->get_type()->get_width(); int result_width = ivl_expr_width(e); - + // For === and !== we need to compare std_logic_vectors // rather than signeds vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR, result_width-1, 0); @@ -328,7 +328,7 @@ static vhdl_expr *translate_binary(ivl_expr_t e) bool vectorop = (ltype == VHDL_TYPE_SIGNED || ltype == VHDL_TYPE_UNSIGNED) && (rtype == VHDL_TYPE_SIGNED || rtype == VHDL_TYPE_UNSIGNED); - + // May need to resize the left or right hand side or change the // signedness if (vectorop) { @@ -425,7 +425,7 @@ static vhdl_expr *translate_binary(ivl_expr_t e) result = translate_shift(lhs, rhs, VHDL_BINOP_SRA); else result = translate_shift(lhs, rhs, VHDL_BINOP_SR); - break; + break; case '^': result = translate_numeric(lhs, rhs, VHDL_BINOP_XOR); break; @@ -463,7 +463,7 @@ static vhdl_expr *translate_select(ivl_expr_t e) return NULL; ivl_expr_t o2 = ivl_expr_oper2(e); - if (o2) { + if (o2) { vhdl_expr *base = translate_expr(ivl_expr_oper2(e)); if (NULL == base) return NULL; @@ -528,7 +528,7 @@ static vhdl_expr *translate_ufunc(ivl_expr_t e) const char *funcname = ivl_scope_tname(defscope); - vhdl_type *rettype = + vhdl_type *rettype = vhdl_type::type_for(ivl_expr_width(e), ivl_expr_signed(e) != 0); vhdl_fcall *fcall = new vhdl_fcall(funcname, rettype); @@ -539,18 +539,18 @@ static vhdl_expr *translate_ufunc(ivl_expr_t e) delete fcall; return NULL; } - + // Ensure the parameter has the correct VHDL type // Parameter number is i + 1 since 0th parameter is return value ivl_signal_t param_sig = ivl_scope_port(defscope, i + 1); vhdl_type *param_type = vhdl_type::type_for(ivl_signal_width(param_sig), ivl_signal_signed(param_sig) != 0); - + fcall->add_expr(param->cast(param_type)); delete param_type; } - + return fcall; } @@ -565,7 +565,7 @@ static vhdl_expr *translate_ternary(ivl_expr_t e) sf = SF_TERNARY_SIGNED; else sf = SF_TERNARY_UNSIGNED; - + require_support_function(sf); vhdl_expr *test = translate_expr(ivl_expr_oper1(e)); @@ -576,20 +576,20 @@ static vhdl_expr *translate_ternary(ivl_expr_t e) vhdl_type boolean(VHDL_TYPE_BOOLEAN); test = test->cast(&boolean); - + vhdl_fcall *fcall = new vhdl_fcall(support_function::function_name(sf), vhdl_type::type_for(width, issigned)); fcall->add_expr(test); fcall->add_expr(true_part); fcall->add_expr(false_part); - + return fcall; } static vhdl_expr *translate_concat(ivl_expr_t e) { - vhdl_type *rtype = + vhdl_type *rtype = vhdl_type::type_for(ivl_expr_width(e), ivl_expr_signed(e) != 0); vhdl_binop_expr *concat = new vhdl_binop_expr(VHDL_BINOP_CONCAT, rtype); @@ -716,11 +716,11 @@ vhdl_expr *translate_time_expr(ivl_expr_t e) if (time->get_type()->get_name() != VHDL_TYPE_TIME) { vhdl_type integer(VHDL_TYPE_INTEGER); time = time->cast(&integer); - + vhdl_expr *ns1 = scale_time(get_active_entity(), 1); return new vhdl_binop_expr(time, VHDL_BINOP_MULT, ns1, vhdl_type::time()); } else // Translating IVL_EX_DELAY will always return a time type - return time; + return time; } diff --git a/tgt-vhdl/logic.cc b/tgt-vhdl/logic.cc index b27f69ce2..4efe3cc33 100644 --- a/tgt-vhdl/logic.cc +++ b/tgt-vhdl/logic.cc @@ -36,11 +36,11 @@ static vhdl_expr *inputs_to_expr(vhdl_scope *scope, vhdl_binop_t op, // the program has already been type checked vhdl_binop_expr *gate = new vhdl_binop_expr(op, vhdl_type::std_logic()); - + int npins = ivl_logic_pins(log); for (int i = 1; i < npins; i++) { ivl_nexus_t input = ivl_logic_pin(log, i); - + gate->add_expr(readable_ref(scope, input)); } @@ -57,7 +57,7 @@ static vhdl_expr *input_to_expr(vhdl_scope *scope, vhdl_unaryop_t op, assert(input); vhdl_expr *operand = readable_ref(scope, input); - return new vhdl_unaryop_expr(op, operand, vhdl_type::std_logic()); + return new vhdl_unaryop_expr(op, operand, vhdl_type::std_logic()); } static void bufif_logic(vhdl_arch *arch, ivl_net_logic_t log, bool if0) @@ -65,7 +65,7 @@ static void bufif_logic(vhdl_arch *arch, ivl_net_logic_t log, bool if0) ivl_nexus_t output = ivl_logic_pin(log, 0); vhdl_var_ref *lhs = nexus_to_var_ref(arch->get_scope(), output); assert(lhs); - + vhdl_expr *val = readable_ref(arch->get_scope(), ivl_logic_pin(log, 1)); vhdl_expr *sel = readable_ref(arch->get_scope(), ivl_logic_pin(log, 2)); @@ -80,7 +80,7 @@ static void bufif_logic(vhdl_arch *arch, ivl_net_logic_t log, bool if0) vhdl_binop_t op = if0 ? VHDL_BINOP_EQ : VHDL_BINOP_NEQ; cmp = new vhdl_binop_expr(sel, op, zero, NULL); } - + ivl_signal_t sig = find_signal_named(lhs->get_name(), arch->get_scope()); char zbit; switch (ivl_signal_type(sig)) { @@ -107,12 +107,12 @@ static void bufif_logic(vhdl_arch *arch, ivl_net_logic_t log, bool if0) static void comb_udp_logic(vhdl_arch *arch, ivl_net_logic_t log) { ivl_udp_t udp = ivl_logic_udp(log); - + // As with regular case statements, the expression in a // `with .. select' statement must be "locally static". // This is achieved by first combining the inputs into // a temporary - + ostringstream ss; ss << ivl_logic_basename(log) << "_Tmp"; int msb = ivl_udp_nin(udp) - 1; @@ -149,11 +149,11 @@ static void comb_udp_logic(vhdl_arch *arch, ivl_net_logic_t log) // Ensure the select statement completely covers the input space // or some strict VHDL compilers will complain ws->add_default(new vhdl_const_bit('X')); - + int nrows = ivl_udp_rows(udp); for (int i = 0; i < nrows; i++) { const char *row = ivl_udp_row(udp, i); - + vhdl_expr *value = new vhdl_const_bit(row[nin]); vhdl_expr *cond = new vhdl_const_bits(row, nin, false); @@ -189,11 +189,11 @@ static void seq_udp_logic(vhdl_arch *arch, ivl_net_logic_t log) int msb = ivl_udp_nin(udp) - 1; vhdl_type *tmp_type = vhdl_type::std_logic_vector(msb, 0); proc->get_scope()->add_decl(new vhdl_var_decl("UDP_Inputs", tmp_type)); - + // Concatenate the inputs into a single expression that can be // used as the test in a case statement (this can't be inserted // directly into the case statement due to the requirement that - // the test expression be "locally static") + // the test expression be "locally static") int nin = ivl_udp_nin(udp); vhdl_expr *tmp_rhs = NULL; if (nin == 1) { @@ -217,7 +217,7 @@ static void seq_udp_logic(vhdl_arch *arch, ivl_net_logic_t log) proc->get_container()->add_stmt (new vhdl_assign_stmt(new vhdl_var_ref("UDP_Inputs", NULL), tmp_rhs)); - + arch->add_stmt(proc); } @@ -273,18 +273,18 @@ void draw_logic(vhdl_arch *arch, ivl_net_logic_t log) udp_logic(arch, log); break; default: - { + { // The output is always pin zero ivl_nexus_t output = ivl_logic_pin(log, 0); vhdl_var_ref *lhs = nexus_to_var_ref(arch->get_scope(), output); vhdl_expr *rhs = translate_logic_inputs(arch->get_scope(), log); vhdl_cassign_stmt *ass = new vhdl_cassign_stmt(lhs, rhs); - + ivl_expr_t delay = ivl_logic_delay(log, 1); if (delay) ass->set_after(translate_time_expr(delay)); - + arch->add_stmt(ass); } } diff --git a/tgt-vhdl/lpm.cc b/tgt-vhdl/lpm.cc index 67c09d569..c68d6bebe 100644 --- a/tgt-vhdl/lpm.cc +++ b/tgt-vhdl/lpm.cc @@ -47,7 +47,7 @@ static vhdl_expr *concat_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm) vhdl_type::type_for(ivl_lpm_width(lpm), ivl_lpm_signed(lpm) != 0); vhdl_binop_expr *expr = new vhdl_binop_expr(VHDL_BINOP_CONCAT, result_type); - + for (int i = ivl_lpm_size(lpm) - 1; i >= 0; i--) { vhdl_expr *e = readable_ref(scope, ivl_lpm_data(lpm, i)); if (NULL == e) { @@ -67,7 +67,7 @@ static vhdl_expr *binop_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm, vhdl_binop vhdl_type *result_type = vhdl_type::type_for(out_width, ivl_lpm_signed(lpm) != 0); vhdl_binop_expr *expr = new vhdl_binop_expr(op, result_type); - + for (int i = 0; i < 2; i++) { vhdl_expr *e = readable_ref(scope, ivl_lpm_data(lpm, i)); if (NULL == e) { @@ -77,16 +77,16 @@ static vhdl_expr *binop_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm, vhdl_binop expr->add_expr(e->cast(result_type)); } - + if (op == VHDL_BINOP_MULT) { // Need to resize the output to the desired size, // as this does not happen automatically in VHDL - + vhdl_fcall *resize = new vhdl_fcall("Resize", vhdl_type::nsigned(out_width)); resize->add_expr(expr); resize->add_expr(new vhdl_const_int(out_width)); - + return resize; } else @@ -106,7 +106,7 @@ static vhdl_expr *rel_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm, vhdl_binop_t delete lhs; return NULL; } - + // Ensure LHS and RHS are the same type if (lhs->get_type() != rhs->get_type()) rhs = rhs->cast(lhs->get_type()); @@ -122,20 +122,20 @@ static vhdl_expr *part_select_vp_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm) vhdl_var_ref *selfrom = readable_ref(scope, ivl_lpm_data(lpm, 0)); if (NULL == selfrom) return NULL; - + vhdl_expr *off = part_select_base(scope, lpm);; if (NULL == off) return NULL; if (selfrom->get_type()->get_width() > 1) selfrom->set_slice(off, ivl_lpm_width(lpm) - 1); - + return selfrom; } static vhdl_expr *part_select_pv_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm) -{ +{ return readable_ref(scope, ivl_lpm_data(lpm, 0)); } @@ -171,13 +171,13 @@ static vhdl_expr *reduction_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm, require_support_function(f); vhdl_fcall *fcall = new vhdl_fcall(support_function::function_name(f), vhdl_type::std_logic()); - - vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR); + + vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR); fcall->add_expr(ref->cast(&std_logic_vector)); - + result = fcall; - } - + } + if (invert) return new vhdl_unaryop_expr (VHDL_UNARYOP_NOT, result, vhdl_type::std_logic()); @@ -199,12 +199,12 @@ static vhdl_expr *array_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm) ivl_signal_t array = ivl_lpm_array(lpm); if (!seen_signal_before(array)) return NULL; - + const char *renamed = get_renamed_signal(array).c_str(); - + vhdl_decl *adecl = scope->get_decl(renamed); assert(adecl); - + vhdl_type *atype = new vhdl_type(*adecl->get_type()); vhdl_expr *select = readable_ref(scope, ivl_lpm_select(lpm)); @@ -212,11 +212,11 @@ static vhdl_expr *array_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm) delete atype; return NULL; } - + vhdl_var_ref *ref = new vhdl_var_ref(renamed, atype); vhdl_type integer(VHDL_TYPE_INTEGER); ref->set_slice(select->cast(&integer)); - + return ref; } @@ -226,8 +226,8 @@ static vhdl_expr *shift_lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm, vhdl_expr *lhs = readable_ref(scope, ivl_lpm_data(lpm, 0)); vhdl_expr *rhs = readable_ref(scope, ivl_lpm_data(lpm, 1)); if (!lhs || !rhs) - return NULL; - + return NULL; + // The RHS must be an integer vhdl_type integer(VHDL_TYPE_INTEGER); vhdl_expr *r_cast = rhs->cast(&integer); @@ -311,7 +311,7 @@ static int draw_mux_lpm(vhdl_arch *arch, ivl_lpm_t lpm) } vhdl_scope *scope = arch->get_scope(); - + vhdl_expr *s0 = readable_ref(scope, ivl_lpm_data(lpm, 0)); vhdl_expr *s1 = readable_ref(scope, ivl_lpm_data(lpm, 1)); @@ -319,7 +319,7 @@ static int draw_mux_lpm(vhdl_arch *arch, ivl_lpm_t lpm) vhdl_expr *b1 = new vhdl_const_bit('1'); vhdl_expr *t1 = new vhdl_binop_expr(sel, VHDL_BINOP_EQ, b1, vhdl_type::boolean()); - + vhdl_var_ref *out = nexus_to_var_ref(scope, ivl_lpm_q(lpm)); // Make sure s0 and s1 have the same type as the output @@ -337,11 +337,11 @@ int draw_lpm(vhdl_arch *arch, ivl_lpm_t lpm) { if (ivl_lpm_type(lpm) == IVL_LPM_MUX) return draw_mux_lpm(arch, lpm); - + vhdl_expr *f = lpm_to_expr(arch->get_scope(), lpm); if (NULL == f) return 1; - + vhdl_var_ref *out = nexus_to_var_ref(arch->get_scope(), ivl_lpm_q(lpm)); if (ivl_lpm_type(lpm) == IVL_LPM_PART_PV) { vhdl_expr *off = part_select_base(arch->get_scope(), lpm); @@ -357,16 +357,16 @@ int draw_lpm(vhdl_arch *arch, ivl_lpm_t lpm) bool bool_to_logic = out->get_type()->get_name() == VHDL_TYPE_STD_LOGIC && f->get_type()->get_name() == VHDL_TYPE_BOOLEAN; - + if (bool_to_logic) { vhdl_cassign_stmt* s = new vhdl_cassign_stmt(out, new vhdl_const_bit('0')); s->add_condition(new vhdl_const_bit('1'), f); arch->add_stmt(s); } - else + else arch->add_stmt(new vhdl_cassign_stmt(out, f->cast(out->get_type()))); - + return 0; } diff --git a/tgt-vhdl/process.cc b/tgt-vhdl/process.cc index 9440b25cf..4660ea98b 100644 --- a/tgt-vhdl/process.cc +++ b/tgt-vhdl/process.cc @@ -33,7 +33,7 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc) { set_active_entity(ent); - + // Create a new process and store it in the entity's // architecture. This needs to be done first or the // parent link won't be valid (and draw_stmt needs this @@ -45,7 +45,7 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc) // into the declarations vhdl_proc->get_scope()->set_initializing (ivl_process_type(proc) == IVL_PR_INITIAL); - + ivl_statement_t stmt = ivl_process_stmt(proc); int rc = draw_stmt(vhdl_proc, vhdl_proc->get_container(), stmt); if (rc != 0) @@ -61,13 +61,13 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc) // Get rid of any useless `wait for 0 ns's at the end of the process prune_wait_for_0(vhdl_proc->get_container()); - // The above pruning might have removed all logic from the process + // The above pruning might have removed all logic from the process if (!vhdl_proc->get_container()->empty()) { vhdl_wait_stmt *wait = new vhdl_wait_stmt(); vhdl_proc->get_container()->add_stmt(wait); } } - + // Add a comment indicating where it came from ivl_scope_t scope = ivl_process_scope(proc); const char *type = ivl_process_type(proc) == IVL_PR_INITIAL @@ -90,21 +90,21 @@ extern "C" int draw_process(ivl_process_t proc, void *cd) if (!is_default_scope_instance(scope)) return 0; // Ignore this process at it's not in a scope that // we're using to generate code - + debug_msg("Translating process in scope type %s (%s:%d)", ivl_scope_tname(scope), ivl_process_file(proc), ivl_process_lineno(proc)); - + // Skip over any generate and begin scopes until we find // the module that contains them - this is where we will // generate the process while (ivl_scope_type(scope) == IVL_SCT_GENERATE || ivl_scope_type(scope) == IVL_SCT_BEGIN) scope = ivl_scope_parent(scope); - + assert(ivl_scope_type(scope) == IVL_SCT_MODULE); vhdl_entity *ent = find_entity(scope); assert(ent != NULL); - + return generate_vhdl_process(ent, proc); } diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc index 6097b41e5..1cd47f91e 100644 --- a/tgt-vhdl/scope.cc +++ b/tgt-vhdl/scope.cc @@ -42,7 +42,7 @@ struct scope_nexus_t { string tmpname; // A new temporary signal list connect; // Other signals to wire together }; - + /* * This structure is stored in the private part of each nexus. * It stores a scope_nexus_t for each VHDL scope which is @@ -76,11 +76,11 @@ static scope_nexus_t *visible_nexus(nexus_private_t *priv, vhdl_scope *scope) */ static void link_scope_to_nexus_signal(nexus_private_t *priv, vhdl_scope *scope, ivl_signal_t sig, unsigned pin) -{ +{ scope_nexus_t *sn; if ((sn = visible_nexus(priv, scope))) { assert(sn->tmpname == ""); - + // Remember to connect this signal up later // If one of the signals is a input, make sure the input is not being driven if (ivl_signal_port(sn->sig) == IVL_SIP_INPUT) @@ -126,16 +126,16 @@ static ivl_signal_type_t signal_type_of_nexus(ivl_nexus_t nex, int &width) { ivl_signal_type_t out = IVL_SIT_TRI; width = 0; - + for (unsigned idx = 0; idx < ivl_nexus_ptrs(nex); idx += 1) { ivl_signal_type_t stype; ivl_nexus_ptr_t ptr = ivl_nexus_ptr(nex, idx); ivl_signal_t sig = ivl_nexus_ptr_sig(ptr); if (sig == 0) continue; - + width = ivl_signal_width(sig); - + stype = ivl_signal_type(sig); if (stype == IVL_SIT_TRI) continue; @@ -143,7 +143,7 @@ static ivl_signal_type_t signal_type_of_nexus(ivl_nexus_t nex, int &width) continue; out = stype; } - + return out; } @@ -151,11 +151,11 @@ static ivl_signal_type_t signal_type_of_nexus(ivl_nexus_t nex, int &width) * Generates VHDL code to fully represent a nexus. */ void draw_nexus(ivl_nexus_t nexus) -{ +{ nexus_private_t *priv = new nexus_private_t; int nexus_signal_width = -1; priv->const_driver = NULL; - + int nptrs = ivl_nexus_ptrs(nexus); // Number of drivers for this nexus @@ -164,9 +164,9 @@ void draw_nexus(ivl_nexus_t nexus) // First pass through connect all the signals up for (int i = 0; i < nptrs; i++) { ivl_nexus_ptr_t nexus_ptr = ivl_nexus_ptr(nexus, i); - + ivl_signal_t sig; - if ((sig = ivl_nexus_ptr_sig(nexus_ptr))) { + if ((sig = ivl_nexus_ptr_sig(nexus_ptr))) { vhdl_scope *scope = find_scope_for_signal(sig); if (scope) { unsigned pin = ivl_nexus_ptr_pin(nexus_ptr); @@ -181,7 +181,7 @@ void draw_nexus(ivl_nexus_t nexus) // inputs and outputs for (int i = 0; i < nptrs; i++) { ivl_nexus_ptr_t nexus_ptr = ivl_nexus_ptr(nexus, i); - + ivl_net_logic_t log; ivl_lpm_t lpm; ivl_net_const_t con; @@ -189,10 +189,10 @@ void draw_nexus(ivl_nexus_t nexus) ivl_scope_t log_scope = ivl_logic_scope(log); if (!is_default_scope_instance(log_scope)) continue; - + vhdl_entity *ent = find_entity(log_scope); assert(ent); - + vhdl_scope *vhdl_scope = ent->get_arch()->get_scope(); if (visible_nexus(priv, vhdl_scope)) { // Already seen this signal in vhdl_scope @@ -201,7 +201,7 @@ void draw_nexus(ivl_nexus_t nexus) // Create a temporary signal to connect it to the nexus vhdl_type *type = vhdl_type::type_for(ivl_logic_width(log), false); - + ostringstream ss; ss << "LO" << ivl_logic_basename(log); vhdl_scope->add_decl(new vhdl_signal_decl(ss.str().c_str(), type)); @@ -218,7 +218,7 @@ void draw_nexus(ivl_nexus_t nexus) ivl_scope_t lpm_scope = ivl_lpm_scope(lpm); vhdl_entity *ent = find_entity(lpm_scope); assert(ent); - + vhdl_scope *vhdl_scope = ent->get_arch()->get_scope(); if (visible_nexus(priv, vhdl_scope)) { // Already seen this signal in vhdl_scope @@ -235,7 +235,7 @@ void draw_nexus(ivl_nexus_t nexus) lpm_temp_width = nexus_signal_width; else lpm_temp_width = ivl_lpm_width(lpm); - + vhdl_type *type = vhdl_type::type_for(lpm_temp_width, ivl_lpm_signed(lpm) != 0); ostringstream ss; @@ -243,7 +243,7 @@ void draw_nexus(ivl_nexus_t nexus) if (!vhdl_scope->have_declared(ss.str())) vhdl_scope->add_decl(new vhdl_signal_decl(ss.str().c_str(), type)); - + link_scope_to_nexus_tmp(priv, vhdl_scope, ss.str()); } @@ -274,7 +274,7 @@ void draw_nexus(ivl_nexus_t nexus) if (ndrivers == 0) { char def = 0; int width; - + switch (signal_type_of_nexus(nexus, width)) { case IVL_SIT_TRI: case IVL_SIT_UWIRE: @@ -305,7 +305,7 @@ void draw_nexus(ivl_nexus_t nexus) priv->const_driver = new vhdl_const_bit(def); } } - + // Save the private data in the nexus ivl_nexus_set_private(nexus, priv); } @@ -316,10 +316,10 @@ void draw_nexus(ivl_nexus_t nexus) */ static void seen_nexus(ivl_nexus_t nexus) { - if (ivl_nexus_get_private(nexus) == NULL) + if (ivl_nexus_get_private(nexus) == NULL) draw_nexus(nexus); } - + /* * Translate a nexus to a variable reference. Given a nexus and a * scope, this function returns a reference to a signal that is @@ -332,18 +332,18 @@ static void seen_nexus(ivl_nexus_t nexus) vhdl_var_ref *nexus_to_var_ref(vhdl_scope *scope, ivl_nexus_t nexus) { seen_nexus(nexus); - + nexus_private_t *priv = static_cast(ivl_nexus_get_private(nexus)); unsigned pin; string renamed(visible_nexus_signal_name(priv, scope, &pin)); - + vhdl_decl *decl = scope->get_decl(renamed); assert(decl); vhdl_type *type = new vhdl_type(*(decl->get_type())); vhdl_var_ref *ref = new vhdl_var_ref(renamed.c_str(), type); - + if (decl->get_type()->get_name() == VHDL_TYPE_ARRAY) ref->set_slice(new vhdl_const_int(pin), 0); @@ -355,7 +355,7 @@ vhdl_var_ref *nexus_to_var_ref(vhdl_scope *scope, ivl_nexus_t nexus) vhdl_var_ref* readable_ref(vhdl_scope* scope, ivl_nexus_t nex) { vhdl_var_ref* ref = nexus_to_var_ref(scope, nex); - + vhdl_decl* decl = scope->get_decl(ref->get_name()); decl->ensure_readable(); @@ -369,10 +369,10 @@ vhdl_var_ref* readable_ref(vhdl_scope* scope, ivl_nexus_t nex) static void declare_logic(vhdl_arch *arch, ivl_scope_t scope) { debug_msg("Declaring logic in scope type %s", ivl_scope_tname(scope)); - + int nlogs = ivl_scope_logs(scope); for (int i = 0; i < nlogs; i++) - draw_logic(arch, ivl_scope_log(scope, i)); + draw_logic(arch, ivl_scope_log(scope, i)); } // Replace consecutive underscores with a single underscore @@ -422,7 +422,7 @@ static string valid_entity_name(const string& module_name) name = "module" + name; if (*name.rbegin() == '_') name += "module"; - + if (is_vhdl_reserved_word(name)) name += "_module"; @@ -434,7 +434,7 @@ static string valid_entity_name(const string& module_name) ss.str(""); ss << name << i++; } - + return ss.str(); } @@ -445,7 +445,7 @@ string make_safe_name(ivl_signal_t sig) if (ivl_signal_local(sig)) base = "tmp" + base; - + if (base[0] == '_') base = "sig" + base; @@ -454,14 +454,14 @@ string make_safe_name(ivl_signal_t sig) // Can't have two consecutive underscores replace_consecutive_underscores(base); - + // A signal name may not be the same as a component name if (find_entity(base) != NULL) base += "_sig"; if (is_vhdl_reserved_word(base)) base += "_sig"; - + return base; } @@ -478,7 +478,7 @@ static void avoid_name_collision(string& name, vhdl_scope* scope) ss.str(""); ss << name << i++; } while (scope->name_collides(ss.str())); - + name = ss.str(); } } @@ -495,24 +495,24 @@ static string genvar_unique_suffix(ivl_scope_t scope) for (unsigned i = 0; i < ivl_scope_params(scope); i++) { ivl_parameter_t param = ivl_scope_param(scope, i); ivl_expr_t e = ivl_parameter_expr(param); - + if (ivl_expr_type(e) == IVL_EX_NUMBER) { vhdl_expr* value = translate_expr(e); assert(value); - + value = value->cast(vhdl_type::integer()); - + suffix << "_" << ivl_parameter_basename(param); value->emit(suffix, 0); - + delete value; } else { error("Only numeric genvars supported at the moment"); return "_ERROR"; // Never used - } + } } - + scope = ivl_scope_parent(scope); } @@ -528,33 +528,33 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, string name(make_safe_name(sig)); name += genvar_unique_suffix(scope); avoid_name_collision(name, ent->get_arch()->get_scope()); - + rename_signal(sig, name); - + vhdl_type *sig_type; unsigned dimensions = ivl_signal_dimensions(sig); if (dimensions > 0) { // Arrays are implemented by generating a separate type // declaration for each array, and then declaring a // signal of that type - + if (dimensions > 1) { error("> 1 dimension arrays not implemented yet"); return; } - + string type_name = name + "_Type"; vhdl_type *base_type = vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0); - + int lsb = ivl_signal_array_base(sig); int msb = lsb + ivl_signal_array_count(sig) - 1; - + vhdl_type *array_type = vhdl_type::array_of(base_type, type_name, msb, lsb); vhdl_decl *array_decl = new vhdl_type_decl(type_name.c_str(), array_type); ent->get_arch()->get_scope()->add_decl(array_decl); - + sig_type = new vhdl_type(*array_type); } else { @@ -562,15 +562,15 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, ivl_signal_signed(sig) != 0, 0, ivl_signal_type(sig) == IVL_SIT_UWIRE); - + } - + ivl_signal_port_t mode = ivl_signal_port(sig); switch (mode) { case IVL_SIP_NONE: { vhdl_decl *decl = new vhdl_signal_decl(name.c_str(), sig_type); - + ostringstream ss; if (ivl_signal_local(sig)) { ss << "Temporary created at " << ivl_signal_file(sig) << ":" @@ -580,7 +580,7 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, << ivl_signal_lineno(sig); } decl->set_comment(ss.str().c_str()); - + ent->get_arch()->get_scope()->add_decl(decl); } break; @@ -591,10 +591,10 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, case IVL_SIP_OUTPUT: { vhdl_port_decl *decl = - new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_OUT); + new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_OUT); ent->get_scope()->add_decl(decl); } - + if (ivl_signal_type(sig) == IVL_SIT_REG) { // A registered output // In Verilog the output and reg can have the @@ -604,11 +604,11 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, std::string newname(name); newname += "_Reg"; rename_signal(sig, newname.c_str()); - + vhdl_type *reg_type = new vhdl_type(*sig_type); ent->get_arch()->get_scope()->add_decl (new vhdl_signal_decl(newname.c_str(), reg_type)); - + // Create a concurrent assignment statement to // connect the register to the output ent->get_arch()->add_stmt @@ -633,17 +633,17 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, static void declare_signals(vhdl_entity *ent, ivl_scope_t scope) { debug_msg("Declaring signals in scope type %s", ivl_scope_tname(scope)); - + int nsigs = ivl_scope_sigs(scope); for (int i = 0; i < nsigs; i++) { - ivl_signal_t sig = ivl_scope_sig(scope, i); + ivl_signal_t sig = ivl_scope_sig(scope, i); if (ivl_signal_port(sig) != IVL_SIP_NONE) declare_one_signal(ent, sig, scope); } - + for (int i = 0; i < nsigs; i++) { - ivl_signal_t sig = ivl_scope_sig(scope, i); + ivl_signal_t sig = ivl_scope_sig(scope, i); if (ivl_signal_port(sig) == IVL_SIP_NONE) declare_one_signal(ent, sig, scope); @@ -669,7 +669,7 @@ static void declare_lpm(vhdl_arch *arch, ivl_scope_t scope) */ static void map_signal(ivl_signal_t to, vhdl_entity *parent, vhdl_comp_inst *inst) -{ +{ // TODO: Work for multiple words ivl_nexus_t nexus = ivl_signal_nex(to, 0); seen_nexus(nexus); @@ -699,14 +699,14 @@ static void map_signal(ivl_signal_t to, vhdl_entity *parent, && !arch_scope->have_declared(name + "_Readable")) { vhdl_decl* tmp_decl = new vhdl_signal_decl(name + "_Readable", ref->get_type()); - + // Add a comment to explain what this is for tmp_decl->set_comment("Needed to connect outputs"); - + arch_scope->add_decl(tmp_decl); parent->get_arch()->add_stmt (new vhdl_cassign_stmt(from_decl->make_ref(), tmp_decl->make_ref())); - + map_to = tmp_decl->make_ref(); } else @@ -719,7 +719,7 @@ static void map_signal(ivl_signal_t to, vhdl_entity *parent, else { // This nexus isn't attached to anything in the parent return; - } + } inst->map_port(name, map_to); } @@ -734,7 +734,7 @@ static void port_map(ivl_scope_t scope, vhdl_entity *parent, int nsigs = ivl_scope_sigs(scope); for (int i = 0; i < nsigs; i++) { ivl_signal_t sig = ivl_scope_sig(scope, i); - + ivl_signal_port_t mode = ivl_signal_port(sig); switch (mode) { case IVL_SIP_NONE: @@ -744,10 +744,10 @@ static void port_map(ivl_scope_t scope, vhdl_entity *parent, case IVL_SIP_OUTPUT: case IVL_SIP_INOUT: map_signal(sig, parent, inst); - break; + break; default: assert(false); - } + } } } @@ -788,9 +788,9 @@ static int draw_function(ivl_scope_t scope, ivl_scope_t parent) vhdl_type *sigtype = vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0); - + string signame(make_safe_name(sig)); - + switch (ivl_signal_port(sig)) { case IVL_SIP_INPUT: func->add_param(new vhdl_param_decl(signame.c_str(), sigtype)); @@ -807,30 +807,30 @@ static int draw_function(ivl_scope_t scope, ivl_scope_t parent) // Only expecting inputs and outputs assert(false); } - + remember_signal(sig, func->get_scope()); rename_signal(sig, signame); } - + int nsigs = ivl_scope_sigs(scope); for (int i = 0; i < nsigs; i++) { - ivl_signal_t sig = ivl_scope_sig(scope, i); + ivl_signal_t sig = ivl_scope_sig(scope, i); if (ivl_signal_port(sig) == IVL_SIP_NONE) { vhdl_type *sigtype = vhdl_type::type_for( ivl_signal_width(sig), ivl_signal_signed(sig) != 0); - + string signame(make_safe_name(sig)); func->get_scope()->add_decl( new vhdl_var_decl(signame, sigtype)); - + remember_signal(sig, func->get_scope()); rename_signal(sig, signame); } } - + // Non-blocking assignment not allowed in functions func->get_scope()->set_allow_signal_assignment(false); @@ -849,8 +849,8 @@ static int draw_function(ivl_scope_t scope, ivl_scope_t parent) ss << "Generated from function " << funcname << " at " << ivl_scope_def_file(scope) << ":" << ivl_scope_def_lineno(scope); func->set_comment(ss.str().c_str()); - - ent->get_arch()->get_scope()->add_decl(func); + + ent->get_arch()->get_scope()->add_decl(func); return 0; } @@ -867,14 +867,14 @@ static int draw_task(ivl_scope_t scope, ivl_scope_t parent) assert(ent); const char *taskname = ivl_scope_tname(scope); - + int nsigs = ivl_scope_sigs(scope); for (int i = 0; i < nsigs; i++) { - ivl_signal_t sig = ivl_scope_sig(scope, i); + ivl_signal_t sig = ivl_scope_sig(scope, i); vhdl_type *sigtype = vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0); - + string signame(make_safe_name(sig)); // Check this signal isn't declared in the outer scope @@ -889,13 +889,13 @@ static int draw_task(ivl_scope_t scope, ivl_scope_t parent) ss << "Declared at " << ivl_signal_file(sig) << ":" << ivl_signal_lineno(sig) << " (in task " << taskname << ")"; decl->set_comment(ss.str().c_str()); - - ent->get_arch()->get_scope()->add_decl(decl); - + + ent->get_arch()->get_scope()->add_decl(decl); + remember_signal(sig, ent->get_arch()->get_scope()); rename_signal(sig, signame); } - + return 0; } @@ -908,7 +908,7 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth) // The type name will become the entity name const string tname = valid_entity_name(ivl_scope_tname(scope)); - + // Verilog does not have the entity/architecture distinction // so we always create a pair and associate the architecture // with the entity for convenience (this also means that we @@ -925,10 +925,10 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth) ss << "Generated from Verilog module " << ivl_scope_tname(scope) << " (" << ivl_scope_def_file(scope) << ":" << ivl_scope_def_lineno(scope) << ")"; - + arch->set_comment(ss.str()); ent->set_comment(ss.str()); - + remember_entity(ent, scope); } @@ -939,13 +939,13 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth) extern "C" int draw_skeleton_scope(ivl_scope_t scope, void *_unused) { static int depth = 0; - + if (seen_this_scope_type(scope)) return 0; // Already generated a skeleton for this scope type - + debug_msg("Initial visit to scope type %s at depth %d", ivl_scope_tname(scope), depth); - + switch (ivl_scope_type(scope)) { case IVL_SCT_MODULE: create_skeleton_entity_for(scope, depth); @@ -968,7 +968,7 @@ extern "C" int draw_all_signals(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance - + if (ivl_scope_type(scope) == IVL_SCT_MODULE) { vhdl_entity *ent = find_entity(scope); assert(ent); @@ -983,7 +983,7 @@ extern "C" int draw_all_signals(ivl_scope_t scope, void *_parent) ivl_scope_t parent = ivl_scope_parent(scope); while (ivl_scope_type(parent) == IVL_SCT_GENERATE) parent = ivl_scope_parent(scope); - + vhdl_entity* ent = find_entity(parent); assert(ent); @@ -1000,7 +1000,7 @@ extern "C" int draw_functions(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance - + ivl_scope_t parent = static_cast(_parent); if (ivl_scope_type(scope) == IVL_SCT_FUNCTION) { if (draw_function(scope, parent) != 0) @@ -1024,9 +1024,9 @@ extern "C" int draw_constant_drivers(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance - + ivl_scope_children(scope, draw_constant_drivers, scope); - + if (ivl_scope_type(scope) == IVL_SCT_MODULE) { vhdl_entity *ent = find_entity(scope); assert(ent); @@ -1034,7 +1034,7 @@ extern "C" int draw_constant_drivers(ivl_scope_t scope, void *_parent) int nsigs = ivl_scope_sigs(scope); for (int i = 0; i < nsigs; i++) { ivl_signal_t sig = ivl_scope_sig(scope, i); - + for (unsigned j = ivl_signal_array_base(sig); j < ivl_signal_array_count(sig); j++) { @@ -1042,7 +1042,7 @@ extern "C" int draw_constant_drivers(ivl_scope_t scope, void *_parent) ivl_nexus_t nex = ivl_signal_nex(sig, j); if (!nex) continue; // skip virtual pins seen_nexus(nex); - + nexus_private_t *priv = static_cast(ivl_nexus_get_private(nex)); assert(priv); @@ -1052,11 +1052,11 @@ extern "C" int draw_constant_drivers(ivl_scope_t scope, void *_parent) if (priv->const_driver && ivl_signal_port(sig) != IVL_SIP_INPUT) { // Don't drive inputs assert(j == 0); // TODO: Make work for more words - + vhdl_var_ref *ref = nexus_to_var_ref(arch_scope, nex); - + ent->get_arch()->add_stmt - (new vhdl_cassign_stmt(ref, priv->const_driver)); + (new vhdl_cassign_stmt(ref, priv->const_driver)); priv->const_driver = NULL; } @@ -1065,7 +1065,7 @@ extern "C" int draw_constant_drivers(ivl_scope_t scope, void *_parent) scope_nexus_t *sn = visible_nexus(priv, arch_scope); // Make sure we don't drive inputs - if (ivl_signal_port(sn->sig) != IVL_SIP_INPUT) { + if (ivl_signal_port(sn->sig) != IVL_SIP_INPUT) { for (list::const_iterator it = sn->connect.begin(); it != sn->connect.end(); ++it) { @@ -1075,20 +1075,20 @@ extern "C" int draw_constant_drivers(ivl_scope_t scope, void *_parent) vhdl_type* ltype = vhdl_type::type_for(ivl_signal_width(*it), ivl_signal_signed(*it)); - + vhdl_var_ref *rref = new vhdl_var_ref(get_renamed_signal(sn->sig).c_str(), rtype); vhdl_var_ref *lref = new vhdl_var_ref(get_renamed_signal(*it).c_str(), ltype); - + // Make sure the LHS and RHS have the same type vhdl_expr* rhs = rref->cast(lref->get_type()); - + ent->get_arch()->add_stmt(new vhdl_cassign_stmt(lref, rhs)); } } - sn->connect.clear(); - } + sn->connect.clear(); + } } } @@ -1099,7 +1099,7 @@ extern "C" int draw_all_logic_and_lpm(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance - + if (ivl_scope_type(scope) == IVL_SCT_MODULE) { vhdl_entity *ent = find_entity(scope); assert(ent); @@ -1110,40 +1110,40 @@ extern "C" int draw_all_logic_and_lpm(ivl_scope_t scope, void *_parent) declare_lpm(ent->get_arch(), scope); } set_active_entity(NULL); - } + } return ivl_scope_children(scope, draw_all_logic_and_lpm, scope); } extern "C" int draw_hierarchy(ivl_scope_t scope, void *_parent) -{ +{ if (ivl_scope_type(scope) == IVL_SCT_MODULE && _parent) { ivl_scope_t parent = static_cast(_parent); // Skip over any containing generate scopes while (ivl_scope_type(parent) == IVL_SCT_GENERATE) parent = ivl_scope_parent(parent); - + if (!is_default_scope_instance(parent)) return 0; // Not generating code for the parent instance so // don't generate for the child - + vhdl_entity *ent = find_entity(scope); assert(ent); - + vhdl_entity *parent_ent = find_entity(parent); assert(parent_ent); vhdl_arch *parent_arch = parent_ent->get_arch(); assert(parent_arch != NULL); - + // Create a forward declaration for it vhdl_scope *parent_scope = parent_arch->get_scope(); if (!parent_scope->have_declared(ent->get_name())) { vhdl_decl *comp_decl = vhdl_component_decl::component_decl_for(ent); parent_arch->get_scope()->add_decl(comp_decl); } - + // And an instantiation statement string inst_name(ivl_scope_basename(scope)); inst_name += genvar_unique_suffix(ivl_scope_parent(scope)); @@ -1154,13 +1154,13 @@ extern "C" int draw_hierarchy(ivl_scope_t scope, void *_parent) // Would produce an invalid instance name inst_name += "_inst"; } - + // Need to replace any [ and ] characters that result // from generate statements string::size_type loc = inst_name.find('[', 0); if (loc != string::npos) inst_name.erase(loc, 1); - + loc = inst_name.find(']', 0); if (loc != string::npos) inst_name.erase(loc, 1); @@ -1177,7 +1177,7 @@ extern "C" int draw_hierarchy(ivl_scope_t scope, void *_parent) // Make sure the name doesn't collide with anything we've // already declared avoid_name_collision(inst_name, parent_arch->get_scope()); - + vhdl_comp_inst *inst = new vhdl_comp_inst(inst_name.c_str(), ent->get_name().c_str()); port_map(scope, parent_ent, inst); @@ -1186,15 +1186,15 @@ extern "C" int draw_hierarchy(ivl_scope_t scope, void *_parent) ss << "Generated from instantiation at " << ivl_scope_file(scope) << ":" << ivl_scope_lineno(scope); inst->set_comment(ss.str().c_str()); - + parent_arch->add_stmt(inst); - } + } return ivl_scope_children(scope, draw_hierarchy, scope); } int draw_scope(ivl_scope_t scope, void *_parent) -{ +{ int rc = draw_skeleton_scope(scope, _parent); if (rc != 0) return rc; @@ -1205,7 +1205,7 @@ int draw_scope(ivl_scope_t scope, void *_parent) rc = draw_all_logic_and_lpm(scope, _parent); if (rc != 0) - return rc; + return rc; rc = draw_hierarchy(scope, _parent); if (rc != 0) @@ -1218,7 +1218,7 @@ int draw_scope(ivl_scope_t scope, void *_parent) rc = draw_constant_drivers(scope, _parent); if (rc != 0) return rc; - + return 0; } diff --git a/tgt-vhdl/state.cc b/tgt-vhdl/state.cc index 0ced93f27..8de2f33d0 100644 --- a/tgt-vhdl/state.cc +++ b/tgt-vhdl/state.cc @@ -53,7 +53,7 @@ using namespace std; * provides a mechanism for renaming signals -- i.e. when * an output has the same name as register: valid in Verilog * but not in VHDL, so two separate signals need to be - * defined. + * defined. */ struct signal_defn_t { std::string renamed; // The name of the VHDL signal @@ -64,7 +64,7 @@ struct signal_defn_t { // These are stored in a list rather than a set so the first // entity added will correspond to the first (top) Verilog module // encountered and hence it will appear first in the output file. -static entity_list_t g_entities; +static entity_list_t g_entities; // Store the mapping of ivl scope names to entity names typedef map scope_name_map_t; @@ -145,7 +145,7 @@ ivl_signal_t find_signal_named(const std::string &name, const vhdl_scope *scope) // Compare the name of an entity against a string struct cmp_ent_name { cmp_ent_name(const string& n) : name_(n) {} - + bool operator()(const vhdl_entity* ent) const { return ent->get_name() == name_; @@ -156,7 +156,7 @@ struct cmp_ent_name { // Find an entity given its name. vhdl_entity* find_entity(const string& name) -{ +{ entity_list_t::const_iterator it = find_if(g_entities.begin(), g_entities.end(), cmp_ent_name(name)); @@ -176,7 +176,7 @@ vhdl_entity* find_entity(ivl_scope_t scope) // Skip over generate scopes while (ivl_scope_type(scope) == IVL_SCT_GENERATE) scope = ivl_scope_parent(scope); - + assert(ivl_scope_type(scope) == IVL_SCT_MODULE); scope_name_map_t::iterator it = g_scope_names.find(ivl_scope_tname(scope)); @@ -213,7 +213,7 @@ void free_all_vhdl_objects() size_t total = vhdl_element::total_allocated(); debug_msg("%d total bytes used for VHDL syntax objects", total); - + g_entities.clear(); } diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc index 774ce9d06..77952521e 100644 --- a/tgt-vhdl/stmt.cc +++ b/tgt-vhdl/stmt.cc @@ -40,7 +40,7 @@ * An alternative is to use the VHPI interface supported by * some VHDL simulators and implement the $finish functionality * in C. This function can be enabled with the flag - * -puse-vhpi-finish=1. + * -puse-vhpi-finish=1. */ static int draw_stask_finish(vhdl_procedural *proc, stmt_container *container, ivl_statement_t stmt) @@ -53,7 +53,7 @@ static int draw_stask_finish(vhdl_procedural *proc, stmt_container *container, else { container->add_stmt(new vhdl_assert_stmt("SIMULATION FINISHED")); } - + return 0; } @@ -93,7 +93,7 @@ static int draw_stask(vhdl_procedural *proc, stmt_container *container, * * If this block has its own scope with local variables then these * are added to the process as local variables and the statements - * are generated as above. + * are generated as above. */ static int draw_block(vhdl_procedural *proc, stmt_container *container, ivl_statement_t stmt, bool is_last) @@ -111,7 +111,7 @@ static int draw_block(vhdl_procedural *proc, stmt_container *container, (new vhdl_var_decl(make_safe_name(sig), type)); } } - + int count = ivl_stmt_block_count(stmt); for (int i = 0; i < count; i++) { ivl_statement_t stmt_i = ivl_stmt_block_stmt(stmt, i); @@ -138,7 +138,7 @@ static int draw_noop(vhdl_procedural *proc, stmt_container *container, * we might as well not emit the first zero-time wait. */ void prune_wait_for_0(stmt_container *container) -{ +{ vhdl_wait_stmt *wait0; stmt_container::stmt_list_t &stmts = container->get_stmts(); while (stmts.size() > 0 @@ -167,13 +167,13 @@ static vhdl_var_ref *make_assign_lhs(ivl_lval_t lval, vhdl_scope *scope) if (e_off) { if ((base = translate_expr(e_off)) == NULL) return NULL; - + vhdl_type integer(VHDL_TYPE_INTEGER); base = base->cast(&integer); } - + unsigned lval_width = ivl_lval_width(lval); - + string signame(get_renamed_signal(sig)); vhdl_decl *decl = scope->get_decl(signame); assert(decl); @@ -197,7 +197,7 @@ static vhdl_var_ref *make_assign_lhs(ivl_lval_t lval, vhdl_scope *scope) // ...and use this new variable as the assignment LHS decl = shadow_decl; } - + vhdl_type *ltype = new vhdl_type(*decl->get_type()); vhdl_var_ref *lval_ref = new vhdl_var_ref(decl->get_name(), ltype); if (base) { @@ -221,7 +221,7 @@ static bool assignment_lvals(ivl_statement_t stmt, vhdl_procedural *proc, return false; lvals.push_back(lhs); - } + } return true; } @@ -239,7 +239,7 @@ assign_for(vhdl_decl::assign_type_t atype, vhdl_var_ref *lhs, vhdl_expr *rhs) return new vhdl_assign_stmt(lhs, rhs); case vhdl_decl::ASSIGN_NONBLOCK: return new vhdl_nbassign_stmt(lhs, rhs); - } + } assert(false); return NULL; } @@ -289,7 +289,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, if (lvals.size() == 1) { vhdl_var_ref *lhs = lvals.front(); rhs = rhs->cast(lhs->get_type()); - + ivl_expr_t i_delay; vhdl_expr *after = NULL; if ((i_delay = ivl_stmt_delay_expr(stmt)) != NULL) @@ -300,7 +300,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, // a variable, etc?) vhdl_decl *decl = proc->get_scope()->get_decl(lhs->get_name()); assign_type = decl->assignment_type(); - + // A small optimisation is to expand ternary RHSs into an // if statement (eliminates a function call and produces // more idiomatic code) @@ -308,7 +308,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, rhs2 = rhs2->cast(lhs->get_type()); vhdl_var_ref *lhs2 = make_assign_lhs(ivl_stmt_lval(stmt, 0), proc->get_scope()); - + vhdl_expr *test = translate_expr(ivl_expr_oper1(rval)); if (NULL == test) return; @@ -344,7 +344,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, // declaration as initialisers. This optimisation is only // performed on assignments of constant values to prevent // ordering problems. - + // This also has another application: If this is an `initial' // process and we haven't yet generated a `wait' statement then // moving the assignment to the initialization preserves the @@ -360,7 +360,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, && !decl->has_initial() && rhs->constant() && decl->get_type()->get_name() != VHDL_TYPE_ARRAY) { - + // If this assignment is not in the top-level container // it will not be made on all paths through the code // This precludes any future extraction of an initialiser @@ -379,7 +379,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, vhdl_abstract_assign_stmt *a = assign_for(decl->assignment_type(), lhs, rhs); container->add_stmt(a); - + if (after != NULL) a->set_after(after); } @@ -396,16 +396,16 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, proc->get_scope()->add_decl(tmp_decl); container->add_stmt(new vhdl_assign_stmt(tmp_decl->make_ref(), rhs)); - + list::iterator it; int width_so_far = 0; for (it = lvals.begin(); it != lvals.end(); ++it) { vhdl_var_ref *tmp_rhs = tmp_decl->make_ref(); - + int lval_width = (*it)->get_type()->get_width(); vhdl_expr *slice_base = new vhdl_const_int(width_so_far); tmp_rhs->set_slice(slice_base, lval_width - 1); - + ivl_expr_t i_delay; vhdl_expr *after = NULL; if ((i_delay = ivl_stmt_delay_expr(stmt)) != NULL) @@ -419,7 +419,7 @@ void make_assignment(vhdl_procedural *proc, stmt_container *container, if (!check_valid_assignment(decl->assignment_type(), proc, stmt)) return; - + vhdl_abstract_assign_stmt *a = assign_for(decl->assignment_type(), *it, tmp_rhs); if (after) @@ -473,7 +473,7 @@ static int draw_assign(vhdl_procedural *proc, stmt_container *container, } else make_assignment(proc, container, stmt, true, assign_type); - + return 0; } @@ -511,7 +511,7 @@ static int draw_delay(vhdl_procedural *proc, stmt_container *container, // Remember that we needed a wait statement so if this is // a process it cannot have a sensitivity list proc->added_wait_stmt(); - + container->add_stmt(wait); // Expand the sub-statement as well @@ -519,12 +519,12 @@ static int draw_delay(vhdl_procedural *proc, stmt_container *container, // is caught here instead if (ivl_statement_type(sub_stmt) != IVL_ST_NOOP) draw_stmt(proc, container, sub_stmt); - + // Any further assignments occur after simulation time 0 // so they cannot be used to initialise signal declarations // (if this scope is an initial process) proc->get_scope()->set_initializing(false); - + return 0; } @@ -582,19 +582,19 @@ static bool draw_synthesisable_wait(vhdl_process *proc, stmt_container *containe { // At the moment this only detects FFs with an asynchronous reset // All other code will fall back on the default draw_wait - + // Store a set of the edge triggered signals // The second item is true if this is positive-edge set edge_triggered; - + const int nevents = ivl_stmt_nevent(stmt); - + for (int i = 0; i < nevents; i++) { ivl_event_t event = ivl_stmt_events(stmt, i); if (ivl_event_nany(event) > 0) return false; - + int npos = ivl_event_npos(event); for (int j = 0; j < npos; j++) edge_triggered.insert(ivl_event_pos(event, j)); @@ -661,13 +661,13 @@ static bool draw_synthesisable_wait(vhdl_process *proc, stmt_container *containe edge = new vhdl_fcall("falling_edge", vhdl_type::boolean()); } assert(edge); - + edge->add_expr(nexus_to_var_ref(proc->get_scope(), *clock_net.begin())); // Draw the clocked branch // For an asynchronous reset we just want this around the else branch, stmt_container *else_container = body->add_elsif(edge); - + draw_stmt(proc, else_container, ivl_stmt_cond_false(sub_stmt)); if (proc->contains_wait_stmt()) { @@ -707,7 +707,7 @@ static bool draw_synthesisable_wait(vhdl_process *proc, stmt_container *containe * The difficulty stems from VHDL's restriction that a process with * a sensitivity list may not contain any `wait' statements: we need * to generate these to accurately model some Verilog statements. - * + * * The steps followed are: * 1) Determine whether this is the top-level statement in the process * 2) If this is top-level, call draw_synthesisable_wait to see if the @@ -753,7 +753,7 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container, return 0; int nevents = ivl_stmt_nevent(stmt); - + bool combinatorial = true; // True if no negedge/posedge events for (int i = 0; i < nevents; i++) { ivl_event_t event = ivl_stmt_events(stmt, i); @@ -770,11 +770,11 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container, vhdl_wait_stmt *wait = NULL; if (proc->contains_wait_stmt() || !is_top_level) - wait = new vhdl_wait_stmt(VHDL_WAIT_ON); - + wait = new vhdl_wait_stmt(VHDL_WAIT_ON); + for (int i = 0; i < nevents; i++) { ivl_event_t event = ivl_stmt_events(stmt, i); - + int nany = ivl_event_nany(event); for (int j = 0; j < nany; j++) { ivl_nexus_t nexus = ivl_event_any(event, j); @@ -803,22 +803,22 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container, stmt_container tmp_container; draw_stmt(proc, &tmp_container, ivl_stmt_sub_stmt(stmt), true); - + for (int i = 0; i < nevents; i++) { ivl_event_t event = ivl_stmt_events(stmt, i); - + int nany = ivl_event_nany(event); for (int j = 0; j < nany; j++) { ivl_nexus_t nexus = ivl_event_any(event, j); vhdl_var_ref *ref = nexus_to_var_ref(proc->get_scope(), nexus); - + ref->set_name(ref->get_name() + "'Event"); test->add_expr(ref); if (!proc->contains_wait_stmt() && is_top_level) proc->add_sensitivity(ref->get_name()); } - + int nneg = ivl_event_nneg(event); for (int j = 0; j < nneg; j++) { ivl_nexus_t nexus = ivl_event_neg(event, j); @@ -826,13 +826,13 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container, vhdl_fcall *detect = new vhdl_fcall("falling_edge", vhdl_type::boolean()); detect->add_expr(ref); - + test->add_expr(detect); if (!proc->contains_wait_stmt() && is_top_level) proc->add_sensitivity(ref->get_name()); } - + int npos = ivl_event_npos(event); for (int j = 0; j < npos; j++) { ivl_nexus_t nexus = ivl_event_pos(event, j); @@ -840,14 +840,14 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container, vhdl_fcall *detect = new vhdl_fcall("rising_edge", vhdl_type::boolean()); detect->add_expr(ref); - + test->add_expr(detect); if (!proc->contains_wait_stmt() && is_top_level) proc->add_sensitivity(ref->get_name()); } } - + if (proc->contains_wait_stmt() || !is_top_level) { container->add_stmt(new vhdl_wait_stmt(VHDL_WAIT_UNTIL, test)); container->move_stmts_from(&tmp_container); @@ -863,9 +863,9 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container, container->add_stmt(edge_detect); } - + } - + return 0; } @@ -875,7 +875,7 @@ static int draw_if(vhdl_procedural *proc, stmt_container *container, vhdl_expr *test = translate_expr(ivl_stmt_cond_expr(stmt)); if (NULL == test) return 1; - + vhdl_if_stmt *vhdif = new vhdl_if_stmt(test); ivl_statement_t cond_true_stmt = ivl_stmt_cond_true(stmt); @@ -887,7 +887,7 @@ static int draw_if(vhdl_procedural *proc, stmt_container *container, draw_stmt(proc, vhdif->get_else_container(), cond_false_stmt, is_last); container->add_stmt(vhdif); - + return 0; } @@ -904,7 +904,7 @@ static vhdl_var_ref *draw_case_test(vhdl_procedural *proc, stmt_container *conta if (typeid(*test) != typeid(vhdl_var_ref)) { const char *tmp_name = "Verilog_Case_Ex"; vhdl_type *test_type = new vhdl_type(*test->get_type()); - + if (!proc->get_scope()->have_declared(tmp_name)) { proc->get_scope()->add_decl (new vhdl_var_decl(tmp_name, new vhdl_type(*test_type))); @@ -925,7 +925,7 @@ static int draw_case(vhdl_procedural *proc, stmt_container *container, vhdl_var_ref *test = draw_case_test(proc, container, stmt); if (NULL == test) return 1; - + vhdl_case_stmt *vhdlcase = new vhdl_case_stmt(test); container->add_stmt(vhdlcase); @@ -933,7 +933,7 @@ static int draw_case(vhdl_procedural *proc, stmt_container *container, // possible case. So make sure we add an 'others' branch // if there isn't a default one. bool have_others = false; - + int nbranches = ivl_stmt_case_count(stmt); for (int i = 0; i < nbranches; i++) { vhdl_expr *when; @@ -947,7 +947,7 @@ static int draw_case(vhdl_procedural *proc, stmt_container *container, when = new vhdl_var_ref("others", NULL); have_others = true; } - + vhdl_case_branch *branch = new vhdl_case_branch(when); vhdlcase->add_branch(branch); @@ -960,8 +960,8 @@ static int draw_case(vhdl_procedural *proc, stmt_container *container, new vhdl_case_branch(new vhdl_var_ref("others", NULL)); others->get_container()->add_stmt(new vhdl_null_stmt()); vhdlcase->add_branch(others); - } - + } + return 0; } @@ -1325,12 +1325,12 @@ int draw_casezx(vhdl_procedural *proc, stmt_container *container, return 1; vhdl_if_stmt *result = NULL; - + int nbranches = ivl_stmt_case_count(stmt); bool is_casez = ivl_statement_type(stmt) == IVL_ST_CASEZ; for (int i = 0; i < nbranches; i++) { stmt_container *where = NULL; - + ivl_expr_t net = ivl_stmt_case_expr(stmt, i); if (net) { vhdl_binop_expr *all = @@ -1377,7 +1377,7 @@ int draw_casezx(vhdl_procedural *proc, stmt_container *container, // We don't actually use the generated `test' expression delete test; - + return 0; } @@ -1393,7 +1393,7 @@ int draw_while(vhdl_procedural *proc, stmt_container *container, int rc = draw_stmt(proc, &tmp_container, ivl_stmt_sub_stmt(stmt)); if (rc != 0) return 1; - + vhdl_expr *test = translate_expr(ivl_stmt_cond_expr(stmt)); if (NULL == test) return 1; @@ -1405,7 +1405,7 @@ int draw_while(vhdl_procedural *proc, stmt_container *container, vhdl_while_stmt *loop = new vhdl_while_stmt(test); draw_stmt(proc, loop->get_container(), ivl_stmt_sub_stmt(stmt)); - + container->add_stmt(loop); return 0; } @@ -1437,7 +1437,7 @@ int draw_repeat(vhdl_procedural *proc, stmt_container *container, container->add_stmt(loop); draw_stmt(proc, loop->get_container(), ivl_stmt_sub_stmt(stmt)); - + return 0; } @@ -1455,7 +1455,7 @@ int draw_utask(vhdl_procedural *proc, stmt_container *container, // TOOD: this completely ignores parameters! draw_stmt(proc, container, ivl_scope_def(tscope), false); - + return 0; } @@ -1473,7 +1473,7 @@ int draw_stmt(vhdl_procedural *proc, stmt_container *container, ivl_statement_t stmt, bool is_last) { assert(stmt); - + switch (ivl_statement_type(stmt)) { case IVL_ST_STASK: return draw_stask(proc, container, stmt); @@ -1523,6 +1523,6 @@ int draw_stmt(vhdl_procedural *proc, stmt_container *container, error("No VHDL translation for statement at %s:%d (type = %d)", ivl_stmt_file(stmt), ivl_stmt_lineno(stmt), ivl_statement_type(stmt)); - return 1; + return 1; } } diff --git a/tgt-vhdl/support.cc b/tgt-vhdl/support.cc index 5001d5bc8..6f16ba762 100644 --- a/tgt-vhdl/support.cc +++ b/tgt-vhdl/support.cc @@ -92,7 +92,7 @@ void support_function::emit_reduction(std::ostream &of, int level, // Emit a VHDL function emulating a Verilog reduction operator // Where op is the corresponding VHDL operator and unit is the // right-unit of the operator - + of << "(X : std_logic_vector) return std_logic is" << nl_string(indent(level)) << "variable R : std_logic := '" << unit << "';" << nl_string(level) @@ -106,7 +106,7 @@ void support_function::emit_reduction(std::ostream &of, int level, void support_function::emit(std::ostream &of, int level) const { of << nl_string(level) << "function " << function_name(type_); - + switch (type_) { case SF_UNSIGNED_TO_BOOLEAN: of << "(X : unsigned) return Boolean is" << nl_string(level) @@ -169,6 +169,6 @@ void support_function::emit(std::ostream &of, int level) const default: assert(false); } - + of << nl_string(level) << "end function;"; } diff --git a/tgt-vhdl/support.hh b/tgt-vhdl/support.hh index 1487cb036..063234be1 100644 --- a/tgt-vhdl/support.hh +++ b/tgt-vhdl/support.hh @@ -52,7 +52,7 @@ private: void emit_ternary(std::ostream &of, int level) const; void emit_reduction(std::ostream &of, int level, const char *op, char unit) const; - + support_function_t type_; }; diff --git a/tgt-vhdl/vhdl.cc b/tgt-vhdl/vhdl.cc index 9c025a3c2..9437517f2 100644 --- a/tgt-vhdl/vhdl.cc +++ b/tgt-vhdl/vhdl.cc @@ -80,7 +80,7 @@ void debug_msg(const char *fmt, ...) va_start(args, fmt); if (std::strcmp(ivl_design_flag(g_design, "debug"), "")) { - std::fputs("[DEBUG] ", stdout); + std::fputs("[DEBUG] ", stdout); std::vprintf(fmt, args); std::putchar('\n'); } @@ -127,10 +127,10 @@ extern "C" int target_design(ivl_design_t des) emit_all_entities(outfile, max_depth); } - + // Clean up free_all_vhdl_objects(); - + return g_errors; } diff --git a/tgt-vhdl/vhdl_element.cc b/tgt-vhdl/vhdl_element.cc index 6c1b5cbd8..21478c952 100644 --- a/tgt-vhdl/vhdl_element.cc +++ b/tgt-vhdl/vhdl_element.cc @@ -40,7 +40,7 @@ std::string nl_string(int level) { std::ostringstream ss; newline(ss, level); - return ss.str(); + return ss.str(); } /* @@ -98,7 +98,7 @@ void vhdl_element::print() const // This records the pointer allocated in a static field of vhdl_element // so we can delete it just before the code generator exits. void* vhdl_element::operator new(size_t size) throw (bad_alloc) -{ +{ // Let the default new handle the allocation void* ptr = ::operator new(size); @@ -115,7 +115,7 @@ void* vhdl_element::operator new(size_t size) throw (bad_alloc) // This just sets the corresponding pointer in vhdl_element::allocated_ // to NULL (since it's safe to delete a NULL pointer). void vhdl_element::operator delete(void* ptr) -{ +{ // Let the default delete handle the deallocation ::operator delete(ptr); diff --git a/tgt-vhdl/vhdl_element.hh b/tgt-vhdl/vhdl_element.hh index 01f15d48d..a324e227d 100644 --- a/tgt-vhdl/vhdl_element.hh +++ b/tgt-vhdl/vhdl_element.hh @@ -48,7 +48,7 @@ public: void* operator new(size_t size) throw (std::bad_alloc); void operator delete(void* ptr); - + virtual void emit(std::ostream &of, int level=0) const = 0; void print() const; diff --git a/tgt-vhdl/vhdl_helper.hh b/tgt-vhdl/vhdl_helper.hh index fb4b5848c..814c5369d 100644 --- a/tgt-vhdl/vhdl_helper.hh +++ b/tgt-vhdl/vhdl_helper.hh @@ -29,8 +29,8 @@ template void emit_children(std::ostream &of, const std::list &children, int level, const char *delim = "", - bool trailing_newline = true) -{ + bool trailing_newline = true) +{ // Don't indent if there are no children if (children.empty()) newline(of, level); diff --git a/tgt-vhdl/vhdl_syntax.cc b/tgt-vhdl/vhdl_syntax.cc index 753da7b37..0391b0137 100644 --- a/tgt-vhdl/vhdl_syntax.cc +++ b/tgt-vhdl/vhdl_syntax.cc @@ -33,12 +33,12 @@ using namespace std; vhdl_scope::vhdl_scope() : parent_(NULL), init_(false), sig_assign_(true) { - + } vhdl_scope::~vhdl_scope() { - + } void vhdl_scope::set_initializing(bool i) @@ -109,7 +109,7 @@ vhdl_entity::vhdl_entity(const string& name, vhdl_arch *arch, int depth__) vhdl_entity::~vhdl_entity() { - + } void vhdl_entity::add_port(vhdl_port_decl *decl) @@ -126,7 +126,7 @@ void vhdl_entity::emit(std::ostream &of, int level) const of << "use ieee.numeric_std.all;" << std::endl; of << "use std.textio.all;" << std::endl; of << std::endl; - + emit_comment(of, level); of << "entity " << name_ << " is"; @@ -136,7 +136,7 @@ void vhdl_entity::emit(std::ostream &of, int level) const emit_children(of, ports_.get_decls(), indent(level), ";"); of << ");"; } - + newline(of, level); of << "end entity; "; blank_line(of, level); // Extra blank line after entities @@ -154,7 +154,7 @@ vhdl_const_time* scale_time(const vhdl_entity* ent, uint64_t t) void vhdl_entity::set_time_units(int units, int precision) { int vhdl_units = std::min(units, precision); - + if (vhdl_units >= -3) time_unit_ = TIME_UNIT_MS; else if (vhdl_units >= -6) @@ -167,7 +167,7 @@ void vhdl_entity::set_time_units(int units, int precision) vhdl_arch::~vhdl_arch() { - + } void vhdl_arch::add_stmt(vhdl_process *proc) @@ -213,7 +213,7 @@ void vhdl_process::emit(std::ostream &of, int level) const if (name_.size() > 0) of << name_ << ": "; of << "process "; - + int num_sens = sens_.size(); if (num_sens > 0) { of << "("; @@ -235,7 +235,7 @@ void vhdl_process::emit(std::ostream &of, int level) const stmt_container::~stmt_container() { - + } void stmt_container::add_stmt(vhdl_seq_stmt *stmt) @@ -257,18 +257,18 @@ void stmt_container::move_stmts_from(stmt_container *other) void stmt_container::emit(std::ostream &of, int level, bool newline) const { - emit_children(of, stmts_, level, "", newline); + emit_children(of, stmts_, level, "", newline); } vhdl_comp_inst::vhdl_comp_inst(const char *inst_name, const char *comp_name) : comp_name_(comp_name), inst_name_(inst_name) { - + } vhdl_comp_inst::~vhdl_comp_inst() { - + } void vhdl_comp_inst::map_port(const string& name, vhdl_expr *expr) @@ -300,7 +300,7 @@ void vhdl_comp_inst::emit(std::ostream &of, int level) const newline(of, indent(level)); of << ")"; } - + of << ";"; } @@ -321,7 +321,7 @@ vhdl_component_decl *vhdl_component_decl::component_decl_for(vhdl_entity *ent) (ent->get_name().c_str()); decl->ports_ = ent->get_scope()->get_decls(); - + return decl; } @@ -337,14 +337,14 @@ void vhdl_component_decl::emit(std::ostream &of, int level) const emit_children(of, ports_, indent(level), ";"); of << ");"; } - + newline(of, level); of << "end component;"; } vhdl_wait_stmt::~vhdl_wait_stmt() { - + } void vhdl_wait_stmt::emit(std::ostream &of, int level) const @@ -379,13 +379,13 @@ void vhdl_wait_stmt::emit(std::ostream &of, int level) const } break; } - + of << ";"; } vhdl_decl::~vhdl_decl() { - + } // Make a reference object to this declaration @@ -401,7 +401,7 @@ const vhdl_type *vhdl_decl::get_type() const } void vhdl_decl::set_initial(vhdl_expr *initial) -{ +{ if (!has_initial_) { assert(initial_ == NULL); initial_ = initial; @@ -412,7 +412,7 @@ void vhdl_decl::set_initial(vhdl_expr *initial) void vhdl_port_decl::emit(std::ostream &of, int level) const { of << name_ << " : "; - + switch (mode_) { case VHDL_PORT_IN: of << "in "; @@ -427,7 +427,7 @@ void vhdl_port_decl::emit(std::ostream &of, int level) const of << "buffer "; break; } - + type_->emit(of, level); } @@ -451,12 +451,12 @@ void vhdl_var_decl::emit(std::ostream &of, int level) const { of << "variable " << name_ << " : "; type_->emit(of, level); - + if (initial_) { of << " := "; initial_->emit(of, level); } - + of << ";"; emit_comment(of, level, true); } @@ -465,12 +465,12 @@ void vhdl_signal_decl::emit(std::ostream &of, int level) const { of << "signal " << name_ << " : "; type_->emit(of, level); - + if (initial_) { of << " := "; initial_->emit(of, level); } - + of << ";"; emit_comment(of, level, true); } @@ -484,7 +484,7 @@ void vhdl_type_decl::emit(std::ostream &of, int level) const vhdl_expr::~vhdl_expr() { - + } void vhdl_expr_list::add_expr(vhdl_expr *e) @@ -494,13 +494,13 @@ void vhdl_expr_list::add_expr(vhdl_expr *e) vhdl_expr_list::~vhdl_expr_list() { - + } void vhdl_expr_list::emit(std::ostream &of, int level) const { of << "("; - + int size = exprs_.size(); std::list::const_iterator it; for (it = exprs_.begin(); it != exprs_.end(); ++it) { @@ -522,7 +522,7 @@ void vhdl_pcall_stmt::emit(std::ostream &of, int level) const vhdl_var_ref::~vhdl_var_ref() { - + } void vhdl_var_ref::set_slice(vhdl_expr *s, int w) @@ -531,21 +531,21 @@ void vhdl_var_ref::set_slice(vhdl_expr *s, int w) slice_ = s; slice_width_ = w; - + vhdl_type_name_t tname = type_->get_name(); if (tname == VHDL_TYPE_ARRAY) { type_ = type_->get_base(); } else { assert(tname == VHDL_TYPE_UNSIGNED || tname == VHDL_TYPE_SIGNED); - + if (w > 0) type_ = new vhdl_type(tname, w); else - type_ = vhdl_type::std_logic(); + type_ = vhdl_type::std_logic(); } } - + void vhdl_var_ref::emit(std::ostream &of, int level) const { of << name_; @@ -565,7 +565,7 @@ void vhdl_const_string::emit(std::ostream &of, int level) const // In some instances a string literal can be ambiguous between // a String type and some other types (e.g. std_logic_vector) // The explicit cast to String removes this ambiguity (although - // isn't always strictly necessary) + // isn't always strictly necessary) of << "String'(\"" << value_ << "\")"; } @@ -583,7 +583,7 @@ void vhdl_fcall::emit(std::ostream &of, int level) const vhdl_abstract_assign_stmt::~vhdl_abstract_assign_stmt() { - + } void vhdl_nbassign_stmt::emit(std::ostream &of, int level) const @@ -596,7 +596,7 @@ void vhdl_nbassign_stmt::emit(std::ostream &of, int level) const of << " after "; after_->emit(of, level); } - + of << ";"; } @@ -609,12 +609,12 @@ void vhdl_assign_stmt::emit(std::ostream &of, int level) const } vhdl_const_bits::vhdl_const_bits(const char *value, int width, bool issigned, - bool qualify) + bool qualify) : vhdl_expr(issigned ? vhdl_type::nsigned(width) : vhdl_type::nunsigned(width), true), qualified_(qualify), signed_(issigned) -{ +{ // Can't rely on value being NULL-terminated while (width--) value_.push_back(*value++); @@ -644,9 +644,9 @@ void vhdl_const_bits::emit(std::ostream &of, int level) const && !has_meta_bits() && bits <= 64 && bits % 4 == 0) { of << "X\"" << hex << setfill('0') << setw(bits / 4) << ival; } - else { + else { of << "\""; - + std::string::const_reverse_iterator it; for (it = value_.rbegin(); it != value_.rend(); ++it) of << vl_to_vhdl_bit(*it); @@ -684,7 +684,7 @@ void vhdl_const_time::emit(std::ostream &of, int level) const vhdl_cassign_stmt::~vhdl_cassign_stmt() { - + } void vhdl_cassign_stmt::add_condition(vhdl_expr *value, vhdl_expr *cond) @@ -709,18 +709,18 @@ void vhdl_cassign_stmt::emit(std::ostream &of, int level) const of << "else "; } rhs_->emit(of, level); - + if (after_) { of << " after "; after_->emit(of, level); } - + of << ";"; } void vhdl_assert_stmt::emit(std::ostream &of, int level) const { - of << "assert false"; // TODO: Allow arbitrary expression + of << "assert false"; // TODO: Allow arbitrary expression of << " report \"" << reason_ << "\" severity failure;"; } @@ -733,7 +733,7 @@ vhdl_if_stmt::vhdl_if_stmt(vhdl_expr *test) vhdl_if_stmt::~vhdl_if_stmt() { - + } stmt_container *vhdl_if_stmt::add_elsif(vhdl_expr *test) @@ -746,7 +746,7 @@ stmt_container *vhdl_if_stmt::add_elsif(vhdl_expr *test) void vhdl_if_stmt::emit(std::ostream &of, int level) const { emit_comment(of, level); - + of << "if "; test_->emit(of, level); of << " then"; @@ -759,7 +759,7 @@ void vhdl_if_stmt::emit(std::ostream &of, int level) const of << " then"; (*it).container->emit(of, level); } - + if (!else_part_.empty()) { of << "else"; else_part_.emit(of, level); @@ -769,7 +769,7 @@ void vhdl_if_stmt::emit(std::ostream &of, int level) const vhdl_unaryop_expr::~vhdl_unaryop_expr() { - + } void vhdl_unaryop_expr::emit(std::ostream &of, int level) const @@ -797,7 +797,7 @@ vhdl_binop_expr::vhdl_binop_expr(vhdl_expr *left, vhdl_binop_t op, vhdl_binop_expr::~vhdl_binop_expr() { - + } void vhdl_binop_expr::add_expr(vhdl_expr *e) @@ -812,7 +812,7 @@ void vhdl_binop_expr::emit(std::ostream &of, int level) const of << "("; - assert(operands_.size() > 0); + assert(operands_.size() > 0); std::list::const_iterator it = operands_.begin(); (*it)->emit(of, level); @@ -826,14 +826,14 @@ void vhdl_binop_expr::emit(std::ostream &of, int level) const of << " " << ops[op_] << " "; (*it)->emit(of, level); - } + } of << ")"; } vhdl_bit_spec_expr::~vhdl_bit_spec_expr() { - + } void vhdl_bit_spec_expr::add_bit(int bit, vhdl_expr *e) @@ -845,7 +845,7 @@ void vhdl_bit_spec_expr::add_bit(int bit, vhdl_expr *e) void vhdl_bit_spec_expr::emit(std::ostream &of, int level) const { of << "("; - + std::list::const_iterator it; it = bits_.begin(); while (it != bits_.end()) { @@ -859,13 +859,13 @@ void vhdl_bit_spec_expr::emit(std::ostream &of, int level) const of << (bits_.empty() ? "" : ", ") << "others => "; others_->emit(of, level); } - + of << ")"; } vhdl_case_branch::~vhdl_case_branch() { - + } void vhdl_case_branch::emit(std::ostream &of, int level) const @@ -878,7 +878,7 @@ void vhdl_case_branch::emit(std::ostream &of, int level) const vhdl_case_stmt::~vhdl_case_stmt() { - + } void vhdl_case_stmt::emit(std::ostream &of, int level) const @@ -897,13 +897,13 @@ void vhdl_case_stmt::emit(std::ostream &of, int level) const else newline(of, level); } - + of << "end case;"; } vhdl_while_stmt::~vhdl_while_stmt() { - + } void vhdl_while_stmt::emit(std::ostream &of, int level) const @@ -923,7 +923,7 @@ void vhdl_loop_stmt::emit(std::ostream &of, int level) const vhdl_for_stmt::~vhdl_for_stmt() { - + } void vhdl_for_stmt::emit(std::ostream &of, int level) const @@ -981,7 +981,7 @@ void vhdl_param_decl::emit(std::ostream &of, int level) const vhdl_with_select_stmt::~vhdl_with_select_stmt() { - + } void vhdl_with_select_stmt::emit(std::ostream &of, int level) const @@ -989,12 +989,12 @@ void vhdl_with_select_stmt::emit(std::ostream &of, int level) const of << "with "; test_->emit(of, level); of << " select"; - emit_comment(of, level, true); + emit_comment(of, level, true); newline(of, indent(level)); out_->emit(of, level); - of << " <= "; - + of << " <= "; + when_list_t::const_iterator it = whens_.begin(); while (it != whens_.end()) { (*it).value->emit(of, level); @@ -1004,7 +1004,7 @@ void vhdl_with_select_stmt::emit(std::ostream &of, int level) const } of << " when "; (*it).cond->emit(of, level); - + if (++it != whens_.end() || others_ != NULL) { of << ","; newline(of, indent(level)); diff --git a/tgt-vhdl/vhdl_syntax.hh b/tgt-vhdl/vhdl_syntax.hh index 961542d99..3f1c78719 100644 --- a/tgt-vhdl/vhdl_syntax.hh +++ b/tgt-vhdl/vhdl_syntax.hh @@ -40,7 +40,7 @@ public: const vhdl_type *get_type() const { return type_; } bool constant() const { return isconst_; } - + vhdl_expr *cast(const vhdl_type *to); virtual vhdl_expr *resize(int newwidth); virtual vhdl_expr *to_boolean(); @@ -63,7 +63,7 @@ public: vhdl_expr *slice = NULL) : vhdl_expr(type), name_(name), slice_(slice), slice_width_(0) {} ~vhdl_var_ref(); - + void emit(std::ostream &of, int level) const; const std::string &get_name() const { return name_; } void set_name(const std::string &name) { name_ = name; } @@ -186,7 +186,7 @@ private: int64_t bits_to_int() const; char sign_bit() const; bool has_meta_bits() const; - + std::string value_; bool qualified_, signed_; }; @@ -243,7 +243,7 @@ private: class vhdl_expr_list : public vhdl_element { public: ~vhdl_expr_list(); - + void emit(std::ostream &of, int level) const; bool empty() const { return exprs_.empty(); } void add_expr(vhdl_expr *e); @@ -315,7 +315,7 @@ public: vhdl_with_select_stmt(vhdl_expr *test, vhdl_var_ref *out) : test_(test), out_(out), others_(NULL) {} ~vhdl_with_select_stmt(); - + void emit(std::ostream &of, int level) const; void add_condition(vhdl_expr *value, vhdl_expr *cond, vhdl_expr *delay=NULL); void add_default(vhdl_expr* value); @@ -343,7 +343,7 @@ public: class stmt_container { public: ~stmt_container(); - + void add_stmt(vhdl_seq_stmt *stmt); void move_stmts_from(stmt_container *other); void emit(std::ostream &of, int level, bool newline=true) const; @@ -369,7 +369,7 @@ public: protected: vhdl_var_ref *lhs_; vhdl_expr *rhs_, *after_; -}; +}; /* @@ -380,7 +380,7 @@ class vhdl_nbassign_stmt : public vhdl_abstract_assign_stmt { public: vhdl_nbassign_stmt(vhdl_var_ref *lhs, vhdl_expr *rhs) : vhdl_abstract_assign_stmt(lhs, rhs) {} - + void emit(std::ostream &of, int level) const; }; @@ -412,7 +412,7 @@ public: vhdl_expr *expr = NULL) : type_(type), expr_(expr) {} ~vhdl_wait_stmt(); - + void emit(std::ostream &of, int level) const; void add_sensitivity(const std::string &s) { sensitivity_.push_back(s); } vhdl_wait_type_t get_type() const { return type_; } @@ -454,7 +454,7 @@ private: vhdl_expr *test; stmt_container *container; }; - + vhdl_expr *test_; stmt_container then_part_, else_part_; std::list elsif_parts_; @@ -495,7 +495,7 @@ private: class vhdl_loop_stmt : public vhdl_seq_stmt { public: virtual ~vhdl_loop_stmt() {} - + stmt_container *get_container() { return &stmts_; } void emit(std::ostream &of, int level) const; private: @@ -519,7 +519,7 @@ public: vhdl_for_stmt(const char *lname, vhdl_expr *from, vhdl_expr *to) : lname_(lname), from_(from), to_(to) {} ~vhdl_for_stmt(); - + void emit(std::ostream &of, int level) const; private: const char *lname_; @@ -534,7 +534,7 @@ private: class vhdl_pcall_stmt : public vhdl_seq_stmt { public: vhdl_pcall_stmt(const char *name) : name_(name) {} - + void emit(std::ostream &of, int level) const; void add_expr(vhdl_expr *e) { exprs_.add_expr(e); } private: @@ -564,12 +564,12 @@ public: // Return a new reference to this declaration vhdl_var_ref* make_ref() const; - + // The different sorts of assignment statement // ASSIGN_CONST is used to generate a variable to shadow a // constant that cannot be assigned to (e.g. a function parameter) enum assign_type_t { ASSIGN_BLOCK, ASSIGN_NONBLOCK, ASSIGN_CONST }; - + // Get the sort of assignment statement to generate for // assignemnts to this declaration // For some sorts of declarations it doesn't make sense @@ -580,7 +580,7 @@ public: // True if this declaration can be read from virtual bool is_readable() const { return true; } - + // Modify this declaration so it can be read from // This does nothing for most declaration types virtual void ensure_readable() {} @@ -592,7 +592,7 @@ protected: }; typedef std::list decl_list_t; - + /* * A forward declaration of a component. At the moment it is assumed @@ -722,7 +722,7 @@ class vhdl_scope { public: vhdl_scope(); ~vhdl_scope(); - + void add_decl(vhdl_decl *decl); void add_forward_decl(vhdl_decl *decl); vhdl_decl *get_decl(const std::string &name) const; @@ -730,7 +730,7 @@ public: bool name_collides(const string& name) const; bool contained_within(const vhdl_scope *other) const; vhdl_scope *get_parent() const; - + bool empty() const { return decls_.empty(); } const decl_list_t &get_decls() const { return decls_; } void set_parent(vhdl_scope *p) { parent_ = p; } @@ -756,7 +756,7 @@ class vhdl_procedural { public: vhdl_procedural() : contains_wait_stmt_(false) {} virtual ~vhdl_procedural() {} - + virtual stmt_container *get_container() { return &stmts_; } virtual vhdl_scope *get_scope() { return &scope_; } @@ -778,7 +778,7 @@ class vhdl_function : public vhdl_decl, public vhdl_procedural { friend class vhdl_forward_fdecl; public: vhdl_function(const char *name, vhdl_type *ret_type); - + virtual void emit(std::ostream &of, int level) const; vhdl_scope *get_scope() { return &variables_; } void add_param(vhdl_param_decl *p) { scope_.add_decl(p); } @@ -848,7 +848,7 @@ public: void set_time_units(int units, int precision); friend vhdl_const_time* scale_time(const vhdl_entity* ent, uint64_t t); - + // Each entity has an associated depth which is how deep in // the Verilog module hierarchy it was found // This is used to limit the maximum depth of modules emitted @@ -857,7 +857,7 @@ private: std::string name_; vhdl_arch *arch_; // Entity may only have a single architecture vhdl_scope ports_; - + // Entities have an associated VHDL time unit // This is used to implement the Verilog timescale directive time_unit_t time_unit_; diff --git a/tgt-vhdl/vhdl_target.h b/tgt-vhdl/vhdl_target.h index 8d99d97a1..3a4aad72a 100644 --- a/tgt-vhdl/vhdl_target.h +++ b/tgt-vhdl/vhdl_target.h @@ -28,11 +28,10 @@ ivl_design_t get_vhdl_design(); vhdl_var_ref *nexus_to_var_ref(vhdl_scope *arch_scope, ivl_nexus_t nexus); vhdl_var_ref* readable_ref(vhdl_scope* scope, ivl_nexus_t nex); string make_safe_name(ivl_signal_t sig); - + int draw_stask_display(vhdl_procedural *proc, stmt_container *container, ivl_statement_t stmt, bool newline = true); -void prune_wait_for_0(stmt_container *container); +void prune_wait_for_0(stmt_container *container); void require_support_function(support_function_t f); #endif /* #ifndef INC_VHDL_TARGET_H */ - diff --git a/tgt-vhdl/vhdl_type.cc b/tgt-vhdl/vhdl_type.cc index c448f6a5e..c53e8e7aa 100644 --- a/tgt-vhdl/vhdl_type.cc +++ b/tgt-vhdl/vhdl_type.cc @@ -86,7 +86,7 @@ std::string vhdl_type::get_string() const case VHDL_TYPE_STD_ULOGIC: return std::string("std_ulogic"); case VHDL_TYPE_STD_LOGIC_VECTOR: - return std::string("std_logic_vector"); + return std::string("std_logic_vector"); case VHDL_TYPE_STRING: return std::string("String"); case VHDL_TYPE_LINE: diff --git a/tgt-vhdl/vhdl_type.hh b/tgt-vhdl/vhdl_type.hh index 9786ab9ad..c374584a7 100644 --- a/tgt-vhdl/vhdl_type.hh +++ b/tgt-vhdl/vhdl_type.hh @@ -57,7 +57,7 @@ public: // Copy constructor vhdl_type(const vhdl_type &other); - + virtual ~vhdl_type(); void emit(std::ostream &of, int level) const; @@ -69,7 +69,7 @@ public: int get_width() const { return msb_ - lsb_ + 1; } int get_msb() const { return msb_; } int get_lsb() const { return lsb_; } - + // Common types static vhdl_type *std_logic(); static vhdl_type *std_ulogic(); diff --git a/tgt-vvp/eval_expr.c b/tgt-vvp/eval_expr.c index 98204b085..335fa7e59 100644 --- a/tgt-vvp/eval_expr.c +++ b/tgt-vvp/eval_expr.c @@ -2589,7 +2589,7 @@ static struct vector_info draw_select_unsized_literal(ivl_expr_t expr, /* If we have an undefined index then just produce a 'bx result. */ fprintf(vvp_out, " %%jmp/1 T_%d.%d, 4;\n", thread_count, lab_x); - /* If the subv result is a magic constant, then make a copy in + /* If the subv result is a magic constant, then make a copy in writable vector space and work from there instead. */ if (subv.base < 4) { res.base = allocate_vector(subv.wid); diff --git a/vvp/array.cc b/vvp/array.cc index be0c86ed6..0258a948f 100644 --- a/vvp/array.cc +++ b/vvp/array.cc @@ -769,7 +769,7 @@ static unsigned vpi_array_is_real(vvp_array_t arr) assert(arr->array_count > 0); struct __vpiRealVar*rsig = vpip_realvar_from_handle(arr->nets[0]); if (rsig) { - struct __vpiSignal*vsig = vpip_signal_from_handle(arr->nets[0]); + struct __vpiSignal*vsig = vpip_signal_from_handle(arr->nets[0]); assert(vsig == 0); return 1U; } @@ -1503,7 +1503,6 @@ void vpip_array_word_change(struct __vpiCallback*cb, vpiHandle obj) void vpip_array_change(struct __vpiCallback*cb, vpiHandle obj) { - struct __vpiArray*arr = ARRAY_HANDLE(obj); cb->extra_data = -1; // This is a callback for every element. cb->next = arr->vpi_callbacks; diff --git a/vvp/concat.cc b/vvp/concat.cc index 76a05715c..a2498536d 100644 --- a/vvp/concat.cc +++ b/vvp/concat.cc @@ -69,7 +69,7 @@ void vvp_fun_concat::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit, vvp_context_t) { assert(bit.size() == wid); - + unsigned pdx = port.port(); if (vwid != wid_[pdx]) { diff --git a/vvp/event.cc b/vvp/event.cc index 570755c3e..ca4027fa8 100644 --- a/vvp/event.cc +++ b/vvp/event.cc @@ -51,7 +51,7 @@ void waitable_hooks_s::run_waiting_threads_(vthread_t&threads) vthread_t tmp = threads; if (tmp == 0) return; threads = 0; - + vthread_schedule_list(tmp); } diff --git a/vvp/examples/vector.vvp b/vvp/examples/vector.vvp index dd8071e79..8e249d098 100644 --- a/vvp/examples/vector.vvp +++ b/vvp/examples/vector.vvp @@ -2,7 +2,7 @@ main .scope module, "main"; -T0 %vpi_call 0 0 "$display", "Display the number: %b", 5'b0zx1; +T0 %vpi_call 0 0 "$display", "Display the number: %b", 5'b0zx1; %end; .thread T0; :file_names 2; diff --git a/vvp/schedule.h b/vvp/schedule.h index 966a9ee7e..11628ca13 100644 --- a/vvp/schedule.h +++ b/vvp/schedule.h @@ -65,9 +65,9 @@ extern void schedule_assign_array_word(vvp_array_t mem, * Create an event to propagate the output of a net. */ extern void schedule_propagate_plucked_vector(vvp_net_t*ptr, - vvp_time64_t delay, + vvp_time64_t delay, const vvp_vector4_t&val, - unsigned adr, unsigned wid); + unsigned adr, unsigned wid); /* * This is very similar to schedule_assign_vector, but generates an diff --git a/vvp/vpi_mcd.cc b/vvp/vpi_mcd.cc index c6ebb24f8..bf8ced53a 100644 --- a/vvp/vpi_mcd.cc +++ b/vvp/vpi_mcd.cc @@ -65,7 +65,7 @@ void vpip_mcd_init(FILE *log) fd_table[idx].fp = NULL; fd_table[idx].filename = NULL; } - + mcd_table[0].fp = stdout; mcd_table[0].filename = strdup("stdout"); diff --git a/vvp/vpi_vthr_vector.cc b/vvp/vpi_vthr_vector.cc index add5b8321..f65d2de97 100644 --- a/vvp/vpi_vthr_vector.cc +++ b/vvp/vpi_vthr_vector.cc @@ -318,7 +318,7 @@ static void vthr_vec_get_value(vpiHandle ref, s_vpi_value*vp) break; case vpiObjTypeVal: - vp->format = vpiVectorVal; + vp->format = vpiVectorVal; case vpiVectorVal: vp->value.vector = (s_vpi_vecval*) need_result_buf((wid+31)/32*sizeof(s_vpi_vecval), RBUF_VAL); diff --git a/vvp/vvp_net.cc b/vvp/vvp_net.cc index 9aada7eab..b8bc706be 100644 --- a/vvp/vvp_net.cc +++ b/vvp/vvp_net.cc @@ -1870,8 +1870,8 @@ void vvp_vector4array_aa::reset_instance(vvp_context_t context) for (unsigned idx = 0 ; idx < words_ ; idx += 1) { if (cell->abits_ptr_) { for (unsigned n = 0 ; n < cnt ; n += 1) { - cell->abits_ptr_[n] = vvp_vector4_t::WORD_X_ABITS; - cell->bbits_ptr_[n] = vvp_vector4_t::WORD_X_BBITS; + cell->abits_ptr_[n] = vvp_vector4_t::WORD_X_ABITS; + cell->bbits_ptr_[n] = vvp_vector4_t::WORD_X_BBITS; } } cell++; diff --git a/vvp/vvp_net.h b/vvp/vvp_net.h index 23c709be8..fa6c42b52 100644 --- a/vvp/vvp_net.h +++ b/vvp/vvp_net.h @@ -65,7 +65,6 @@ typedef void*vvp_context_item_t; inline vvp_context_t vvp_allocate_context(unsigned nitem) { - return (vvp_context_t)malloc((2 + nitem) * sizeof(void*)); } diff --git a/vvp/words.cc b/vvp/words.cc index c4029929d..1236547c9 100644 --- a/vvp/words.cc +++ b/vvp/words.cc @@ -394,7 +394,7 @@ static void __compile_real_net2(vvp_net_t*node, vvp_array_t array, obj = vpip_make_real_var(name, node); compile_vpi_symbol(my_label, obj); } - + // REMOVE ME! Giving the net a label is a legacy of the times // when the .net was a functor of its own. In the long run, we // must fix the code generator to not rely on the label of the