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Fix reduction OR in procedural code

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This commit is contained in:
Nick Gasson
2008-07-20 15:13:20 +01:00
parent 77508b9afa
commit d8351ec1b2
1 changed files with 3 additions and 1 deletions
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tgt-vhdl/expr.cc
+3 -1
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@@ -137,7 +137,9 @@ static vhdl_expr *translate_unary(ivl_expr_t e)
vhdl_fcall *f =
new vhdl_fcall(support_function::function_name(SF_REDUCE_OR),
vhdl_type::std_logic());
f->add_expr(operand);
vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR);
f->add_expr(operand->cast(&std_logic_vector));
if ('N' == opcode)
return new vhdl_unaryop_expr(VHDL_UNARYOP_NOT, f, vhdl_type::std_logic());
else