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Do not change reg to wire in NetAssign_ unless synthesizing.
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@@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netlist.h,v 1.315 2004/06/30 15:32:18 steve Exp $"
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#ident "$Id: netlist.h,v 1.316 2004/08/28 15:08:31 steve Exp $"
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#endif
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/*
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@@ -1427,6 +1427,11 @@ class NetAssign_ {
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NetMemory*mem() const;
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NetVariable*var() const;
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// Mark that the synthesizer has worked with this l-value, so
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// when it is released, the l-value signal should be turned
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// into a wire.
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void turn_sig_to_wire_on_release();
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// This pointer is for keeping simple lists.
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NetAssign_* more;
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@@ -1438,6 +1443,7 @@ class NetAssign_ {
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NetVariable*var_;
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NetExpr*bmux_;
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bool turn_sig_to_wire_on_release_;
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unsigned loff_;
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unsigned lwid_;
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};
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@@ -3343,6 +3349,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.316 2004/08/28 15:08:31 steve
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* Do not change reg to wire in NetAssign_ unless synthesizing.
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*
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* Revision 1.315 2004/06/30 15:32:18 steve
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* nex_output for NetPDelay statements.
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*
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