diff --git a/vhdlpp/entity.cc b/vhdlpp/entity.cc index ffb562fe6..d4d6308db 100644 --- a/vhdlpp/entity.cc +++ b/vhdlpp/entity.cc @@ -56,7 +56,8 @@ static void dump_design_entity(ostream&out, Entity*obj) ; cur != obj->ports.end() ; ++cur) { InterfacePort*item = *cur; out << setw(6) << "" << item->name - << " : " << item->mode << endl; + << " : " << item->mode + << ", type=" << item->type_name << endl; } } } diff --git a/vhdlpp/entity.h b/vhdlpp/entity.h index 46e78e33c..03a62aa1b 100644 --- a/vhdlpp/entity.h +++ b/vhdlpp/entity.h @@ -27,8 +27,12 @@ typedef enum { PORT_NONE=0, PORT_IN, PORT_OUT } port_mode_t; class InterfacePort { public: + // Port direction from the source code. port_mode_t mode; + // Name of the port from the source code perm_string name; + // Name of interface type as given in the source code. + perm_string type_name; }; class Entity { diff --git a/vhdlpp/entity_elaborate.cc b/vhdlpp/entity_elaborate.cc index 8f4fa7d76..699cc732d 100644 --- a/vhdlpp/entity_elaborate.cc +++ b/vhdlpp/entity_elaborate.cc @@ -54,6 +54,16 @@ int Entity::elaborate() ; cur != ports.end() ; ++cur) { InterfacePort*port = *cur; + // FIXME: this is a stub. This port handling code + // currently only supports std_logic signal tyes, + // so just assert that the user asked for std_logic. + if (port->type_name != "std_logic") { + cerr << "sorry: VHDL only supports std_logic ports." + << " Expecting std_logic, but got \"" + << port->type_name << "\"" << endl; + errors += 1; + } + if (sep) cout << sep; else sep = ", "; diff --git a/vhdlpp/parse.y b/vhdlpp/parse.y index 39296be0f..26335ccfd 100644 --- a/vhdlpp/parse.y +++ b/vhdlpp/parse.y @@ -172,6 +172,7 @@ interface_element { InterfacePort*tmp = new InterfacePort; tmp->mode = $3; tmp->name = lex_strings.make($1); + tmp->type_name = lex_strings.make($4); delete[]$1; delete[]$4; $$ = tmp; @@ -180,7 +181,7 @@ interface_element interface_list : interface_list ';' interface_element - { std:list*tmp = $1; + { std::list*tmp = $1; tmp->push_back($3); $$ = tmp; }