Generate correct VHDL signal values

tgt-vhdl/vhdl_helper.hh

@@ -23,6 +23,7 @@
 
 #include <fstream>
 #include <list>
+#include <cassert>
 
 template <class T>
 void emit_children(std::ofstream &of,
@@ -54,4 +55,20 @@ void delete_children(std::list<T*> &children)
    children.clear();
 }
 
+static inline char vl_to_vhdl_bit(char bit)
+{
+   switch (bit) {
+   case '0':
+   case 'Z':
+   case '1':
+      return bit;
+   case 'z':
+      return 'Z';
+   case 'x':
+   case 'X':
+      return 'U';
+   }
+   assert(false);
+}
+
 #endif

tgt-vhdl/vhdl_syntax.cc

@@ -522,14 +522,14 @@ void vhdl_const_bits::emit(std::ofstream &of, int level) const
    // The bits appear to be in reverse order
    std::string::const_reverse_iterator it;
    for (it = value_.rbegin(); it != value_.rend(); ++it)
-      of << *it;
+      of << vl_to_vhdl_bit(*it);
 
    of << "\")";
 }
 
 void vhdl_const_bit::emit(std::ofstream &of, int level) const
 {
-   of << "'" << bit_ << "'";
+   of << "'" << vl_to_vhdl_bit(bit_) << "'";
 }
 
 void vhdl_const_int::emit(std::ofstream &of, int level) const