diff --git a/ivtest/ivltests/br_gh1170.v b/ivtest/ivltests/br_gh1170.v
new file mode 100644
index 000000000..b346d7793
--- /dev/null
+++ b/ivtest/ivltests/br_gh1170.v
@@ -0,0 +1,6 @@
+// Test for GitHub issue #1170
+// tgt-sizer should work with SystemVerilog 2012 ($unit scope)
+module test;
+  logic [7:0] data;
+  assign data = 8'hAA;
+endmodule
diff --git a/ivtest/perl-lib/RegressionList.pm b/ivtest/perl-lib/RegressionList.pm
index a089b4d18..f9ffbb385 100644
--- a/ivtest/perl-lib/RegressionList.pm
+++ b/ivtest/perl-lib/RegressionList.pm
@@ -102,7 +102,7 @@ sub read_regression_list {
             $args{$tname} = "";
         }
         if ($opt ne "std") {
-            $args{$tname} = $opt . $args{$tname};
+            $args{$tname} = $opt . ($args{$tname} ? " " . $args{$tname} : "");
         }
 
         $srcpath{$tname} = $fields[2];
diff --git a/ivtest/regress-synth.list b/ivtest/regress-synth.list
index 3cd91d65f..ca00d4401 100644
--- a/ivtest/regress-synth.list
+++ b/ivtest/regress-synth.list
@@ -137,3 +137,4 @@ ssetclr2		normal			ivltests
 ssetclr3		normal			ivltests
 synth_if_no_else	normal			ivltests
 ufuncsynth1		normal			ivltests
+br_gh1170		CO,-g2012,-tsizer		ivltests
diff --git a/tgt-sizer/sizer.cc b/tgt-sizer/sizer.cc
index cade50217..86ed277f2 100644
--- a/tgt-sizer/sizer.cc
+++ b/tgt-sizer/sizer.cc
@@ -92,6 +92,10 @@ int target_design(ivl_design_t des)
 	// multiple root scopes, we will give isolated numbers for
 	// each and keep then separate.
       for (unsigned idx = 0 ; idx < nroots ; idx += 1) {
+	      // Skip SystemVerilog $unit scope (compilation unit scope)
+	    if (ivl_scope_type(roots[idx]) == IVL_SCT_PACKAGE) {
+		  continue;
+	    }
 	    if (ivl_scope_type(roots[idx]) != IVL_SCT_MODULE) {
 		  fprintf(stderr, "SIZER: The root scope %s must be a module.\n", ivl_scope_basename(roots[idx]));
 		  sizer_errors += 1;