Resize VHDL vector before cast in signed comparison

E.g. $signed(x) > y with x, y different sizes should be

  resize(signed(x), N) > y

Not

  signed(resize(x, N)) > y

As this does not treat the sign bit correctly. Was causing
the signed5 test to fail.

tgt-vhdl/expr.cc

@@ -496,7 +496,7 @@ static vhdl_expr *translate_select(ivl_expr_t e)
       }
    }
    else
-      return from->resize(ivl_expr_width(e));
+      return correct_signedness(from, e)->resize(ivl_expr_width(e));
 }
 
 template <class T>