From d33082bca50429859536199b3c33d7616c571f49 Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Mon, 9 Aug 2010 22:42:43 +0100 Subject: [PATCH] Resize VHDL vector before cast in signed comparison E.g. $signed(x) > y with x, y different sizes should be resize(signed(x), N) > y Not signed(resize(x, N)) > y As this does not treat the sign bit correctly. Was causing the signed5 test to fail. --- tgt-vhdl/expr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tgt-vhdl/expr.cc b/tgt-vhdl/expr.cc index 0b928d4cb..78ce66882 100644 --- a/tgt-vhdl/expr.cc +++ b/tgt-vhdl/expr.cc @@ -496,7 +496,7 @@ static vhdl_expr *translate_select(ivl_expr_t e) } } else - return from->resize(ivl_expr_width(e)); + return correct_signedness(from, e)->resize(ivl_expr_width(e)); } template