Fix tests that used variables/nets before declaring them.

The sdf_interconnect tests just need the code reordering. The
pr1909940 tests were written to test use before declaration, so
now need to be CE tests.
This commit is contained in:
Martin Whitaker 2024-02-19 10:22:31 +00:00
parent 649fbb9a59
commit cd76bd2371
6 changed files with 14 additions and 20 deletions

View File

@ -42,14 +42,14 @@ endmodule
module top; module top;
reg a;
wire b;
initial begin initial begin
$sdf_annotate("ivltests/sdf_interconnect1.sdf", my_design_inst); $sdf_annotate("ivltests/sdf_interconnect1.sdf", my_design_inst);
$monitor("time=%0t a=%h b=%h", $realtime, a, b); $monitor("time=%0t a=%h b=%h", $realtime, a, b);
end end
reg a;
wire b;
initial begin initial begin
#5; #5;
a <= 1'b0; a <= 1'b0;
@ -65,4 +65,3 @@ module top;
); );
endmodule endmodule

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@ -44,14 +44,14 @@ endmodule
module top; module top;
reg a;
wire b;
initial begin initial begin
$sdf_annotate("ivltests/sdf_interconnect2.sdf", my_design_inst); $sdf_annotate("ivltests/sdf_interconnect2.sdf", my_design_inst);
$monitor("time=%0t a=%h b=%h", $realtime, a, b); $monitor("time=%0t a=%h b=%h", $realtime, a, b);
end end
reg a;
wire b;
initial begin initial begin
#5; #5;
a <= 1'b0; a <= 1'b0;
@ -67,4 +67,3 @@ module top;
); );
endmodule endmodule

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@ -87,14 +87,14 @@ endmodule
module top; module top;
reg a, b, c;
wire d;
initial begin initial begin
$sdf_annotate("ivltests/sdf_interconnect3.sdf", my_design_inst); $sdf_annotate("ivltests/sdf_interconnect3.sdf", my_design_inst);
$monitor("time=%0t a=%h b=%h c=%h d=%h", $realtime, a, b, c, d); $monitor("time=%0t a=%h b=%h c=%h d=%h", $realtime, a, b, c, d);
end end
reg a, b, c;
wire d;
initial begin initial begin
#10; #10;
a <= 1'b0; a <= 1'b0;
@ -140,4 +140,3 @@ module top;
); );
endmodule endmodule

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@ -41,14 +41,14 @@ endmodule
module top; module top;
reg [2:0] a;
wire [2:0] b;
initial begin initial begin
$sdf_annotate("ivltests/sdf_interconnect4.sdf", my_design_inst); $sdf_annotate("ivltests/sdf_interconnect4.sdf", my_design_inst);
$monitor("time=%0t a=%b b=%b", $realtime, a, b); $monitor("time=%0t a=%b b=%b", $realtime, a, b);
end end
reg [2:0] a;
wire [2:0] b;
initial begin initial begin
#5; #5;
a <= 3'b000; a <= 3'b000;
@ -64,4 +64,3 @@ module top;
); );
endmodule endmodule

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@ -286,10 +286,6 @@ sv_deferred_assume2 CE,-g2009 ivltests gold=sv_deferred_assume2.gold
# Icarus deviations # Icarus deviations
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Icarus still allows (implicit) declaration after use in some circumstances.
pr1909940 normal ivltests
pr1909940b normal ivltests
# Icarus allows hierarchical references to unnamed generate blocks. # Icarus allows hierarchical references to unnamed generate blocks.
# We should add a warning about this, as it's not strictly allowed. # We should add a warning about this, as it's not strictly allowed.
unnamed_generate_block normal ivltests gold=unnamed_generate_block.gold unnamed_generate_block normal ivltests gold=unnamed_generate_block.gold

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@ -1106,6 +1106,8 @@ pr1903324 normal ivltests
pr1903343 normal ivltests gold=pr1903343.gold pr1903343 normal ivltests gold=pr1903343.gold
pr1903520 normal ivltests pr1903520 normal ivltests
pr1907192 normal ivltests pr1907192 normal ivltests
pr1909940 CE ivltests
pr1909940b CE ivltests
pr1912843 normal ivltests pr1912843 normal ivltests
pr1913918a normal ivltests pr1913918a normal ivltests
pr1913918b normal ivltests pr1913918b normal ivltests