diff --git a/ivtest/ivltests/sdf_interconnect1.v b/ivtest/ivltests/sdf_interconnect1.v
index 91f500539..7f8f44c73 100644
--- a/ivtest/ivltests/sdf_interconnect1.v
+++ b/ivtest/ivltests/sdf_interconnect1.v
@@ -42,14 +42,14 @@ endmodule
 
 module top;
 
+    reg a;
+    wire b;
+
     initial begin
         $sdf_annotate("ivltests/sdf_interconnect1.sdf", my_design_inst);
         $monitor("time=%0t a=%h b=%h", $realtime, a, b);
     end
 
-    reg a;
-    wire b;
-
     initial begin
         #5;
         a <= 1'b0;
@@ -65,4 +65,3 @@ module top;
     );
 
 endmodule
-
diff --git a/ivtest/ivltests/sdf_interconnect2.v b/ivtest/ivltests/sdf_interconnect2.v
index c35523a41..2627398c5 100644
--- a/ivtest/ivltests/sdf_interconnect2.v
+++ b/ivtest/ivltests/sdf_interconnect2.v
@@ -44,14 +44,14 @@ endmodule
 
 module top;
 
+    reg a;
+    wire b;
+
     initial begin
         $sdf_annotate("ivltests/sdf_interconnect2.sdf", my_design_inst);
         $monitor("time=%0t a=%h b=%h", $realtime, a, b);
     end
 
-    reg a;
-    wire b;
-
     initial begin
         #5;
         a <= 1'b0;
@@ -67,4 +67,3 @@ module top;
     );
 
 endmodule
-
diff --git a/ivtest/ivltests/sdf_interconnect3.v b/ivtest/ivltests/sdf_interconnect3.v
index fc501f641..203cc4656 100644
--- a/ivtest/ivltests/sdf_interconnect3.v
+++ b/ivtest/ivltests/sdf_interconnect3.v
@@ -87,14 +87,14 @@ endmodule
 
 module top;
 
+    reg a, b, c;
+    wire d;
+
     initial begin
         $sdf_annotate("ivltests/sdf_interconnect3.sdf", my_design_inst);
         $monitor("time=%0t a=%h b=%h c=%h d=%h", $realtime, a, b, c, d);
     end
 
-    reg a, b, c;
-    wire d;
-
     initial begin
         #10;
         a <= 1'b0;
@@ -140,4 +140,3 @@ module top;
     );
 
 endmodule
-
diff --git a/ivtest/ivltests/sdf_interconnect4.v b/ivtest/ivltests/sdf_interconnect4.v
index 918a34a98..5b6e1be37 100644
--- a/ivtest/ivltests/sdf_interconnect4.v
+++ b/ivtest/ivltests/sdf_interconnect4.v
@@ -41,14 +41,14 @@ endmodule
 
 module top;
 
+    reg [2:0] a;
+    wire [2:0] b;
+
     initial begin
         $sdf_annotate("ivltests/sdf_interconnect4.sdf", my_design_inst);
         $monitor("time=%0t a=%b b=%b", $realtime, a, b);
     end
 
-    reg [2:0] a;
-    wire [2:0] b;
-
     initial begin
         #5;
         a <= 3'b000;
@@ -64,4 +64,3 @@ module top;
     );
 
 endmodule
-
diff --git a/ivtest/regress-ivl1.list b/ivtest/regress-ivl1.list
index 7ba05aba8..af0a5b3e5 100644
--- a/ivtest/regress-ivl1.list
+++ b/ivtest/regress-ivl1.list
@@ -286,10 +286,6 @@ sv_deferred_assume2	CE,-g2009		ivltests gold=sv_deferred_assume2.gold
 # Icarus deviations
 #------------------------------------------------------------------------------
 
-# Icarus still allows (implicit) declaration after use in some circumstances.
-pr1909940		normal			ivltests
-pr1909940b		normal			ivltests
-
 # Icarus allows hierarchical references to unnamed generate blocks.
 # We should add a warning about this, as it's not strictly allowed.
 unnamed_generate_block	normal			ivltests gold=unnamed_generate_block.gold
diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list
index 8dd34a0fa..19ece7d66 100644
--- a/ivtest/regress-vlg.list
+++ b/ivtest/regress-vlg.list
@@ -1106,6 +1106,8 @@ pr1903324		normal			ivltests
 pr1903343		normal			ivltests gold=pr1903343.gold
 pr1903520		normal			ivltests
 pr1907192		normal			ivltests
+pr1909940		CE			ivltests
+pr1909940b		CE			ivltests
 pr1912843		normal			ivltests
 pr1913918a		normal			ivltests
 pr1913918b		normal			ivltests