Duplicate default function/task argument expressions
The default value for a function or task argument is elaborated once and then used for each function invocation where no actual value is provided. This means if a function or task is called multiple times the same NetExpr is passed as a sub-expression to multiple statements or expressions such as the function call. This is causing problems because each expression or statement expects to have exclusive ownership over its sub-expressions. It can for example result in a double free or other undefined behavior. To mitigate this duplicate the default argument expression before it is given as a sub-expression to another expression or statement. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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@ -2954,7 +2954,7 @@ unsigned PECallFunction::elaborate_arguments_(Design*des, NetScope*scope,
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<< "requires SystemVerilog." << endl;
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des->errors += 1;
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}
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parms[pidx] = def->port_defe(pidx);
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parms[pidx] = def->port_defe(pidx)->dup_expr();
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} else {
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missing_parms += 1;
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@ -6573,7 +6573,7 @@ NetExpr* PENewClass::elaborate_expr_constructor_(Design*des, NetScope*scope,
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// Ran out of explicit arguments. Is there a default
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// argument we can use?
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if (NetExpr*tmp = def->port_defe(idx)) {
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parms[idx] = tmp;
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parms[idx] = tmp->dup_expr();
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continue;
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}
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@ -3344,7 +3344,7 @@ NetProc* PChainConstructor::elaborate(Design*des, NetScope*scope) const
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}
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if (NetExpr*tmp = def->port_defe(idx)) {
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parms[idx] = tmp;
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parms[idx] = tmp->dup_expr();
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continue;
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}
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@ -4173,9 +4173,9 @@ NetProc* PCallTask::elaborate_build_call_(Design*des, NetScope*scope,
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"requires SystemVerilog." << endl;
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des->errors += 1;
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}
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rv = def->port_defe(idx);
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rv = def->port_defe(idx)->dup_expr();
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if (lv_type==IVL_VT_BOOL||lv_type==IVL_VT_LOGIC)
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rv = pad_to_width(rv->dup_expr(), wid, *this);
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rv = pad_to_width(rv, wid, *this);
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} else {
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cerr << get_fileline() << ": error: "
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