diff --git a/elab_expr.cc b/elab_expr.cc
index 7db1f21ef..e77d60f7b 100644
--- a/elab_expr.cc
+++ b/elab_expr.cc
@@ -2954,7 +2954,7 @@ unsigned PECallFunction::elaborate_arguments_(Design*des, NetScope*scope,
 			     << "requires SystemVerilog." << endl;
 			des->errors += 1;
 		  }
-		  parms[pidx] = def->port_defe(pidx);
+		  parms[pidx] = def->port_defe(pidx)->dup_expr();
 
 	    } else {
 		  missing_parms += 1;
@@ -6573,7 +6573,7 @@ NetExpr* PENewClass::elaborate_expr_constructor_(Design*des, NetScope*scope,
 	      // Ran out of explicit arguments. Is there a default
 	      // argument we can use?
 	    if (NetExpr*tmp = def->port_defe(idx)) {
-		  parms[idx] = tmp;
+		  parms[idx] = tmp->dup_expr();
 		  continue;
 	    }
 
diff --git a/elaborate.cc b/elaborate.cc
index 95effd6ea..6890e2b77 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -3344,7 +3344,7 @@ NetProc* PChainConstructor::elaborate(Design*des, NetScope*scope) const
 		  }
 
 		  if (NetExpr*tmp = def->port_defe(idx)) {
-			parms[idx] = tmp;
+			parms[idx] = tmp->dup_expr();
 			continue;
 		  }
 
@@ -4173,9 +4173,9 @@ NetProc* PCallTask::elaborate_build_call_(Design*des, NetScope*scope,
 			        "requires SystemVerilog." << endl;
 			des->errors += 1;
 		  }
-		  rv = def->port_defe(idx);
+		  rv = def->port_defe(idx)->dup_expr();
 		  if (lv_type==IVL_VT_BOOL||lv_type==IVL_VT_LOGIC)
-			rv = pad_to_width(rv->dup_expr(), wid, *this);
+			rv = pad_to_width(rv, wid, *this);
 
 	    } else {
 		  cerr << get_fileline() << ": error: "