Add regression tests for automatic terms in cast expressions

Check that a sign, width or type cast expression that contains an automatic
term is detected as such and can not be used as the left-hand side in a
procedural continuous assignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/automatic_error16.v

@@ -0,0 +1,21 @@
+// Check that an expression is correctly detected to contain an automatic
+// variable if the variable is in a SystemVerilog size cast expression.
+
+module automatic_error;
+
+  reg g;
+
+  task automatic auto_task;
+    reg l;
+
+    begin: block
+      assign g = 1'(l);
+    end
+  endtask
+
+  initial begin
+    auto_task;
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/automatic_error17.v

@@ -0,0 +1,22 @@
+// Check that an expression is correctly detected to contain an automatic
+// variable if the variable is in a SystemVerilog sign cast expression.
+
+module test;
+
+  reg g;
+
+  task automatic auto_task;
+    reg l;
+
+    begin: block
+      assign g = signed'(l);
+    end
+
+  endtask
+
+  initial begin
+    auto_task;
+    $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/automatic_error18.v

@@ -0,0 +1,22 @@
+// Check that an expression is correctly detected to contain an automatic
+// variable if the variable is in a SystemVerilog type cast expression.
+
+module test;
+
+  reg g;
+
+  task automatic auto_task;
+    reg l;
+
+    begin: block
+      assign g = reg'(l);
+    end
+
+  endtask
+
+  initial begin
+    auto_task;
+    $display("FAILED");
+  end
+
+endmodule

ivtest/regress-sv.list

@@ -106,6 +106,9 @@ assign_op_real_array_oob normal,-g2009		ivltests
 assign_op_type		normal,-g2009		ivltests
 automatic_error14	CE,-g2005-sv		ivltests
 automatic_error15	CE,-g2005-sv		ivltests
+automatic_error16	CE,-g2005-sv		ivltests
+automatic_error17	CE,-g2005-sv		ivltests
+automatic_error18	CE,-g2005-sv		ivltests
 bitp1			normal,-g2005-sv	ivltests
 bits			normal,-g2005-sv	ivltests
 bits2			normal,-g2005-sv	ivltests