diff --git a/ivtest/ivltests/automatic_error16.v b/ivtest/ivltests/automatic_error16.v new file mode 100644 index 000000000..5d844839a --- /dev/null +++ b/ivtest/ivltests/automatic_error16.v @@ -0,0 +1,21 @@ +// Check that an expression is correctly detected to contain an automatic +// variable if the variable is in a SystemVerilog size cast expression. + +module automatic_error; + + reg g; + + task automatic auto_task; + reg l; + + begin: block + assign g = 1'(l); + end + endtask + + initial begin + auto_task; + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/automatic_error17.v b/ivtest/ivltests/automatic_error17.v new file mode 100644 index 000000000..4615cefae --- /dev/null +++ b/ivtest/ivltests/automatic_error17.v @@ -0,0 +1,22 @@ +// Check that an expression is correctly detected to contain an automatic +// variable if the variable is in a SystemVerilog sign cast expression. + +module test; + + reg g; + + task automatic auto_task; + reg l; + + begin: block + assign g = signed'(l); + end + + endtask + + initial begin + auto_task; + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/automatic_error18.v b/ivtest/ivltests/automatic_error18.v new file mode 100644 index 000000000..d6877158a --- /dev/null +++ b/ivtest/ivltests/automatic_error18.v @@ -0,0 +1,22 @@ +// Check that an expression is correctly detected to contain an automatic +// variable if the variable is in a SystemVerilog type cast expression. + +module test; + + reg g; + + task automatic auto_task; + reg l; + + begin: block + assign g = reg'(l); + end + + endtask + + initial begin + auto_task; + $display("FAILED"); + end + +endmodule diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list index 4825b76a7..e9f4a5ad2 100644 --- a/ivtest/regress-sv.list +++ b/ivtest/regress-sv.list @@ -106,6 +106,9 @@ assign_op_real_array_oob normal,-g2009 ivltests assign_op_type normal,-g2009 ivltests automatic_error14 CE,-g2005-sv ivltests automatic_error15 CE,-g2005-sv ivltests +automatic_error16 CE,-g2005-sv ivltests +automatic_error17 CE,-g2005-sv ivltests +automatic_error18 CE,-g2005-sv ivltests bitp1 normal,-g2005-sv ivltests bits normal,-g2005-sv ivltests bits2 normal,-g2005-sv ivltests