Reject default task/function arguments when parsing traditional Verilog.

elaborate.cc

@@ -3740,7 +3740,7 @@ NetProc* PCallTask::elaborate_build_call_(Design*des, NetScope*scope,
 
 	    } else if (def->port_defe(idx)) {
 		  if (! gn_system_verilog()) {
-			cerr << get_fileline() << ": error: "
+			cerr << get_fileline() << ": internal error: "
 			     << "Found (and using) default task expression "
 			        "requires SystemVerilog." << endl;
 			des->errors += 1;

parse.y

@@ -2133,7 +2133,13 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
   /* This rule matches the [ = <expression> ] part of the tf_port_item rules. */
 
 tf_port_item_expr_opt
-  : '=' expression { $$ = $2; }
+  : '=' expression
+      { if (! gn_system_verilog()) {
+	      yyerror(@1, "error: Task/function default arguments require "
+	                  "SystemVerilog.");
+	}
+	$$ = $2;
+      }
   |   { $$ = 0; }
   ;