From bdd0657140a660f2348557dc6fea45d773d24fbd Mon Sep 17 00:00:00 2001
From: Martin Whitaker <mailing-list@martin-whitaker.me.uk>
Date: Sun, 21 Jun 2015 09:05:39 +0100
Subject: [PATCH] Reject default task/function arguments when parsing
 traditional Verilog.

---
 elaborate.cc |  2 +-
 parse.y      | 12 +++++++++---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/elaborate.cc b/elaborate.cc
index 5a7175bed..2a6a0525f 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -3740,7 +3740,7 @@ NetProc* PCallTask::elaborate_build_call_(Design*des, NetScope*scope,
 
 	    } else if (def->port_defe(idx)) {
 		  if (! gn_system_verilog()) {
-			cerr << get_fileline() << ": error: "
+			cerr << get_fileline() << ": internal error: "
 			     << "Found (and using) default task expression "
 			        "requires SystemVerilog." << endl;
 			des->errors += 1;
diff --git a/parse.y b/parse.y
index 93ecec22e..5ea8250ab 100644
--- a/parse.y
+++ b/parse.y
@@ -2119,7 +2119,7 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
 	      assert(tmp->size()==1);
 	      tmp->front().defe = $5;
 	}
-     }
+      }
 
   /* Rules to match error cases... */
 
@@ -2133,8 +2133,14 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
   /* This rule matches the [ = <expression> ] part of the tf_port_item rules. */
 
 tf_port_item_expr_opt
-  : '=' expression { $$ = $2; }
-  |                { $$ = 0; }
+  : '=' expression
+      { if (! gn_system_verilog()) {
+	      yyerror(@1, "error: Task/function default arguments require "
+	                  "SystemVerilog.");
+	}
+	$$ = $2;
+      }
+  |   { $$ = 0; }
   ;
 
 tf_port_list /* IEEE1800-2005: A.2.7 */