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Reject default task/function arguments when parsing traditional Verilog.

This commit is contained in:
Martin Whitaker 2015-06-21 09:05:39 +01:00
parent 1d279798d8
commit bdd0657140
2 changed files with 10 additions and 4 deletions
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2
elaborate.cc
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@ -3740,7 +3740,7 @@ NetProc* PCallTask::elaborate_build_call_(Design*des, NetScope*scope,
} else if (def->port_defe(idx)) { } else if (def->port_defe(idx)) {
if (! gn_system_verilog()) { if (! gn_system_verilog()) {
cerr << get_fileline() << ": error: " cerr << get_fileline() << ": internal error: "
<< "Found (and using) default task expression " << "Found (and using) default task expression "
"requires SystemVerilog." << endl; "requires SystemVerilog." << endl;
des->errors += 1; des->errors += 1;

8
parse.y
View File

@ -2133,7 +2133,13 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
/* This rule matches the [ = <expression> ] part of the tf_port_item rules. */ /* This rule matches the [ = <expression> ] part of the tf_port_item rules. */
tf_port_item_expr_opt tf_port_item_expr_opt
: '=' expression { $$ = $2; } : '=' expression
{ if (! gn_system_verilog()) {
yyerror(@1, "error: Task/function default arguments require "
"SystemVerilog.");
}
$$ = $2;
}
| { $$ = 0; } | { $$ = 0; }
; ;