Add regression test for module port with array typedef

Check that for a module port with an array type identifier the type is
elaborated in the right scope.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-04-23 09:04:45 +02:00
parent 2385b32cb3
commit bcc0730b6b
3 changed files with 34 additions and 0 deletions

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@ -0,0 +1,32 @@
// Check that an array type identifier used for a module port is elaborated in
// the correct scope.
localparam A = 2;
localparam B = 4;
typedef logic [A-1:0] T[B];
module test (
input T x
);
localparam A = 5;
localparam B = 10;
bit failed = 1'b0;
`define check(expr, val) \
if (expr !== val) begin \
$display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \
failed = 1'b1; \
end
initial begin
`check($size(x, 1), 4);
`check($size(x, 2), 2);
if (!failed) begin
$display("PASSED");
end
end
endmodule

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@ -368,6 +368,7 @@ module_nonansi_struct2 normal,-g2005-sv ivltests
module_nonansi_struct_fail CE,-g2005-sv ivltests
module_output_port_sv_var1 normal,-g2005-sv ivltests
module_output_port_sv_var2 normal,-g2005-sv ivltests
module_port_typedef_array1 normal,-g2005-sv ivltests
named_begin normal,-g2009 ivltests
named_begin_fail CE,-g2009 ivltests
named_fork normal,-g2009 ivltests

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@ -225,6 +225,7 @@ br_ml20171017 CE ivltests
genvar_scopes CE ivltests
meminit2 CE ivltests
memsynth4 CE,-S ivltests # Synthesized net array
module_port_typedef_array1 CE,-g2005-sv ivltests # Module port array
negative_genvar CE ivltests
pr1565544 CE ivltests
pr1657307 CE ivltests