luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Carry strength values from Verilog source to the 

pform and netlist for gates.

 Change vvm constants to use the driver_t to drive
 a constant value. This works better if there are
 multiple drivers on a signal.
This commit is contained in:
steve 2000-05-07 04:37:55 +00:00
parent ca2fd41bb6
commit b90cda1f3f
18 changed files with 797 additions and 444 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
PExpr.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: PExpr.cc,v 1.17 2000/05/04 03:37:58 steve Exp $" #ident "$Id: PExpr.cc,v 1.18 2000/05/07 04:37:55 steve Exp $"
#endif #endif
# include "PExpr.h" # include "PExpr.h"
@ -45,7 +45,9 @@ bool PExpr::is_constant(Module*) const
NetNet* PExpr::elaborate_net(Design*des, const string&path, unsigned, NetNet* PExpr::elaborate_net(Design*des, const string&path, unsigned,
unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long) const unsigned long,
Link::strength_t,
Link::strength_t) const
{ {
cerr << get_line() << ": error: Unable to elaborate `" cerr << get_line() << ": error: Unable to elaborate `"
<< *this << "' as gates." << endl; << *this << "' as gates." << endl;
@ -212,6 +214,14 @@ bool PETernary::is_constant(Module*) const
/* /*
* $Log: PExpr.cc,v $ * $Log: PExpr.cc,v $
* Revision 1.18 2000/05/07 04:37:55 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.17 2000/05/04 03:37:58 steve * Revision 1.17 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move * Add infrastructure for system functions, move
* $time to that structure and add $random. * $time to that structure and add $random.

43
PExpr.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: PExpr.h,v 1.36 2000/05/04 03:37:58 steve Exp $" #ident "$Id: PExpr.h,v 1.37 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include <string> # include <string>
@ -66,7 +66,10 @@ class PExpr : public LineInfo {
unsigned lwidth, unsigned lwidth,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const; unsigned long decay,
Link::strength_t drive0 =Link::STRONG,
Link::strength_t drive1 =Link::STRONG)
const;
// This method elaborates the expression as gates, but // This method elaborates the expression as gates, but
// restricted for use as l-values of continuous assignments. // restricted for use as l-values of continuous assignments.
@ -107,7 +110,9 @@ class PEConcat : public PExpr {
unsigned width, unsigned width,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const; unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetExpr*elaborate_expr(Design*des, NetScope*) const; virtual NetExpr*elaborate_expr(Design*des, NetScope*) const;
virtual bool is_constant(Module*) const; virtual bool is_constant(Module*) const;
@ -159,7 +164,9 @@ class PEIdent : public PExpr {
unsigned lwidth, unsigned lwidth,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const; unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetExpr*elaborate_expr(Design*des, NetScope*) const; virtual NetExpr*elaborate_expr(Design*des, NetScope*) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const; virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
@ -201,7 +208,9 @@ class PENumber : public PExpr {
unsigned lwidth, unsigned lwidth,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const; unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetEConst*elaborate_expr(Design*des, NetScope*) const; virtual NetEConst*elaborate_expr(Design*des, NetScope*) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const; virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
virtual verinum* eval_const(const Design*des, const string&path) const; virtual verinum* eval_const(const Design*des, const string&path) const;
@ -240,7 +249,9 @@ class PEUnary : public PExpr {
unsigned width, unsigned width,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const; unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetEUnary*elaborate_expr(Design*des, NetScope*) const; virtual NetEUnary*elaborate_expr(Design*des, NetScope*) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const; virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
@ -262,7 +273,9 @@ class PEBinary : public PExpr {
unsigned width, unsigned width,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const; unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetEBinary*elaborate_expr(Design*des, NetScope*) const; virtual NetEBinary*elaborate_expr(Design*des, NetScope*) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const; virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
virtual verinum* eval_const(const Design*des, const string&path) const; virtual verinum* eval_const(const Design*des, const string&path) const;
@ -326,9 +339,11 @@ class PETernary : public PExpr {
virtual void dump(ostream&out) const; virtual void dump(ostream&out) const;
virtual NetNet* elaborate_net(Design*des, const string&path, virtual NetNet* elaborate_net(Design*des, const string&path,
unsigned width, unsigned width,
unsigned long rise =0, unsigned long rise,
unsigned long fall =0, unsigned long fall,
unsigned long decay =0) const; unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetETernary*elaborate_expr(Design*des, NetScope*) const; virtual NetETernary*elaborate_expr(Design*des, NetScope*) const;
virtual verinum* eval_const(const Design*des, const string&path) const; virtual verinum* eval_const(const Design*des, const string&path) const;
@ -360,6 +375,14 @@ class PECallFunction : public PExpr {
/* /*
* $Log: PExpr.h,v $ * $Log: PExpr.h,v $
* Revision 1.37 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.36 2000/05/04 03:37:58 steve * Revision 1.36 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move * Add infrastructure for system functions, move
* $time to that structure and add $random. * $time to that structure and add $random.

22
cprop.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: cprop.cc,v 1.8 2000/04/28 21:00:28 steve Exp $" #ident "$Id: cprop.cc,v 1.9 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
@ -29,14 +29,14 @@
* this link are constant. It will also return true if there are no * this link are constant. It will also return true if there are no
* drivers at all. * drivers at all.
*/ */
static bool all_drivers_constant(const NetObj::Link&lnk) static bool all_drivers_constant(const Link&lnk)
{ {
for (const NetObj::Link*cur = lnk.next_link() for (const Link*cur = lnk.next_link()
; *cur != lnk ; cur = cur->next_link()) { ; *cur != lnk ; cur = cur->next_link()) {
if (cur->get_dir() == NetObj::Link::INPUT) if (cur->get_dir() == Link::INPUT)
continue; continue;
if (cur->get_dir() == NetObj::Link::PASSIVE) if (cur->get_dir() == Link::PASSIVE)
continue; continue;
if (! dynamic_cast<const NetConst*>(cur->get_obj())) if (! dynamic_cast<const NetConst*>(cur->get_obj()))
return false; return false;
@ -50,9 +50,9 @@ static bool all_drivers_constant(const NetObj::Link&lnk)
* or Vz if there is no constant. The results of this function are * or Vz if there is no constant. The results of this function are
* only meaningful if all_drivers_constant(lnk) == true. * only meaningful if all_drivers_constant(lnk) == true.
*/ */
static verinum::V driven_value(const NetObj::Link&lnk) static verinum::V driven_value(const Link&lnk)
{ {
for (const NetObj::Link*cur = lnk.next_link() for (const Link*cur = lnk.next_link()
; *cur != lnk ; cur = cur->next_link()) { ; *cur != lnk ; cur = cur->next_link()) {
const NetConst*obj; const NetConst*obj;
@ -319,6 +319,14 @@ void cprop(Design*des)
/* /*
* $Log: cprop.cc,v $ * $Log: cprop.cc,v $
* Revision 1.9 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.8 2000/04/28 21:00:28 steve * Revision 1.8 2000/04/28 21:00:28 steve
* Over agressive signal elimination in constant probadation. * Over agressive signal elimination in constant probadation.
* *

38
design_dump.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: design_dump.cc,v 1.82 2000/05/04 03:37:58 steve Exp $" #ident "$Id: design_dump.cc,v 1.83 2000/05/07 04:37:56 steve Exp $"
#endif #endif
/* /*
@ -42,6 +42,30 @@ static ostream& operator<< (ostream&o, NetBlock::Type t)
return o; return o;
} }
ostream& operator << (ostream&o, Link::strength_t str)
{
switch (str) {
case Link::HIGHZ:
o << "highz";
break;
case Link::WEAK:
o << "weak";
break;
case Link::PULL:
o << "pull";
break;
case Link::STRONG:
o << "strong";
break;
case Link::SUPPLY:
o << "supply";
break;
default:
assert(0);
}
return o;
}
/* Dump a net. This can be a wire or register. */ /* Dump a net. This can be a wire or register. */
void NetNet::dump_net(ostream&o, unsigned ind) const void NetNet::dump_net(ostream&o, unsigned ind) const
{ {
@ -118,7 +142,9 @@ void NetObj::dump_node_pins(ostream&o, unsigned ind) const
o << " O"; o << " O";
break; break;
} }
o << ":";
o << " (" << pin(idx).drive0() << "0 "
<< pin(idx).drive1() << "1):";
unsigned cpin; unsigned cpin;
const NetObj*cur; const NetObj*cur;
@ -929,6 +955,14 @@ void Design::dump(ostream&o) const
/* /*
* $Log: design_dump.cc,v $ * $Log: design_dump.cc,v $
* Revision 1.83 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.82 2000/05/04 03:37:58 steve * Revision 1.82 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move * Add infrastructure for system functions, move
* $time to that structure and add $random. * $time to that structure and add $random.

39
elab_net.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: elab_net.cc,v 1.33 2000/05/03 21:21:36 steve Exp $" #ident "$Id: elab_net.cc,v 1.34 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include "PExpr.h" # include "PExpr.h"
@ -34,7 +34,9 @@ NetNet* PEBinary::elaborate_net(Design*des, const string&path,
unsigned width, unsigned width,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const
{ {
switch (op_) { switch (op_) {
case '*': case '*':
@ -805,7 +807,9 @@ NetNet* PEConcat::elaborate_net(Design*des, const string&path,
unsigned, unsigned,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const
{ {
NetScope*scope = des->find_scope(path); NetScope*scope = des->find_scope(path);
assert(scope); assert(scope);
@ -883,7 +887,9 @@ NetNet* PEIdent::elaborate_net(Design*des, const string&path,
unsigned lwidth, unsigned lwidth,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const
{ {
NetScope*scope = des->find_scope(path); NetScope*scope = des->find_scope(path);
NetNet*sig = des->find_signal(scope, text_); NetNet*sig = des->find_signal(scope, text_);
@ -1141,7 +1147,9 @@ NetNet* PENumber::elaborate_net(Design*des, const string&path,
unsigned lwidth, unsigned lwidth,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const
{ {
NetScope*scope = des->find_scope(path); NetScope*scope = des->find_scope(path);
assert(scope); assert(scope);
@ -1160,8 +1168,11 @@ NetNet* PENumber::elaborate_net(Design*des, const string&path,
num.set(idx, value_->get(idx)); num.set(idx, value_->get(idx));
NetConst*tmp = new NetConst(des->local_symbol(path), num); NetConst*tmp = new NetConst(des->local_symbol(path), num);
for (idx = 0 ; idx < net->pin_count() ; idx += 1) for (idx = 0 ; idx < net->pin_count() ; idx += 1) {
tmp->pin(idx).drive0(drive0);
tmp->pin(idx).drive1(drive1);
connect(net->pin(idx), tmp->pin(idx)); connect(net->pin(idx), tmp->pin(idx));
}
des->add_node(tmp); des->add_node(tmp);
return net; return net;
@ -1237,7 +1248,9 @@ NetNet* PETernary::elaborate_net(Design*des, const string&path,
unsigned width, unsigned width,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const
{ {
NetScope*scope = des->find_scope(path); NetScope*scope = des->find_scope(path);
assert(scope); assert(scope);
@ -1303,7 +1316,9 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
unsigned width, unsigned width,
unsigned long rise, unsigned long rise,
unsigned long fall, unsigned long fall,
unsigned long decay) const unsigned long decay,
Link::strength_t drive0,
Link::strength_t drive1) const
{ {
NetScope*scope = des->find_scope(path); NetScope*scope = des->find_scope(path);
assert(scope); assert(scope);
@ -1447,6 +1462,14 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
/* /*
* $Log: elab_net.cc,v $ * $Log: elab_net.cc,v $
* Revision 1.34 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.33 2000/05/03 21:21:36 steve * Revision 1.33 2000/05/03 21:21:36 steve
* Allow ternary result to be padded to result width. * Allow ternary result to be padded to result width.
* *

34
elaborate.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: elaborate.cc,v 1.168 2000/05/02 16:27:38 steve Exp $" #ident "$Id: elaborate.cc,v 1.169 2000/05/07 04:37:56 steve Exp $"
#endif #endif
/* /*
@ -41,6 +41,24 @@
static const map<string,Module*>* modlist = 0; static const map<string,Module*>* modlist = 0;
static const map<string,PUdp*>* udplist = 0; static const map<string,PUdp*>* udplist = 0;
static Link::strength_t drive_type(PGate::strength_t drv)
{
switch (drv) {
case PGate::HIGHZ:
return Link::HIGHZ;
case PGate::WEAK:
return Link::WEAK;
case PGate::PULL:
return Link::PULL;
case PGate::STRONG:
return Link::STRONG;
case PGate::SUPPLY:
return Link::SUPPLY;
default:
assert(0);
}
return Link::STRONG;
}
void PGate::elaborate(Design*des, const string&path) const void PGate::elaborate(Design*des, const string&path) const
@ -58,6 +76,9 @@ void PGAssign::elaborate(Design*des, const string&path) const
unsigned long rise_time, fall_time, decay_time; unsigned long rise_time, fall_time, decay_time;
eval_delays(des, path, rise_time, fall_time, decay_time); eval_delays(des, path, rise_time, fall_time, decay_time);
Link::strength_t drive0 = drive_type(strength0());
Link::strength_t drive1 = drive_type(strength1());
assert(pin(0)); assert(pin(0));
assert(pin(1)); assert(pin(1));
@ -74,7 +95,8 @@ void PGAssign::elaborate(Design*des, const string&path) const
generated NetNet. */ generated NetNet. */
NetNet*rval = pin(1)->elaborate_net(des, path, NetNet*rval = pin(1)->elaborate_net(des, path,
lval->pin_count(), lval->pin_count(),
rise_time, fall_time, decay_time); rise_time, fall_time, decay_time,
drive0, drive1);
if (rval == 0) { if (rval == 0) {
cerr << get_line() << ": error: Unable to elaborate r-value: " cerr << get_line() << ": error: Unable to elaborate r-value: "
<< *pin(1) << endl; << *pin(1) << endl;
@ -2328,6 +2350,14 @@ Design* elaborate(const map<string,Module*>&modules,
/* /*
* $Log: elaborate.cc,v $ * $Log: elaborate.cc,v $
* Revision 1.169 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.168 2000/05/02 16:27:38 steve * Revision 1.168 2000/05/02 16:27:38 steve
* Move signal elaboration to a seperate pass. * Move signal elaboration to a seperate pass.
* *

14
link_const.cc
View File

@ -17,18 +17,18 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: link_const.cc,v 1.1 2000/04/20 00:28:03 steve Exp $" #ident "$Id: link_const.cc,v 1.2 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
# include "netmisc.h" # include "netmisc.h"
NetConst* link_const_value(NetObj::Link&pin, unsigned&idx) NetConst* link_const_value(Link&pin, unsigned&idx)
{ {
NetConst*robj = 0; NetConst*robj = 0;
unsigned ridx = 0; unsigned ridx = 0;
for (NetObj::Link*cur = pin.next_link() for (Link*cur = pin.next_link()
; *cur != pin ; cur = cur->next_link()) { ; *cur != pin ; cur = cur->next_link()) {
NetConst*tmp; NetConst*tmp;
@ -49,6 +49,14 @@ NetConst* link_const_value(NetObj::Link&pin, unsigned&idx)
/* /*
* $Log: link_const.cc,v $ * $Log: link_const.cc,v $
* Revision 1.2 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.1 2000/04/20 00:28:03 steve * Revision 1.1 2000/04/20 00:28:03 steve
* Catch some simple identity compareoptimizations. * Catch some simple identity compareoptimizations.
* *

391
netlist.cc
View File

File diff suppressed because it is too large Load Diff

381
netlist.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: netlist.h,v 1.135 2000/05/04 03:37:58 steve Exp $" #ident "$Id: netlist.h,v 1.136 2000/05/07 04:37:56 steve Exp $"
#endif #endif
/* /*
@ -35,6 +35,7 @@
# include "svector.h" # include "svector.h"
class Design; class Design;
class Link;
class NetNode; class NetNode;
class NetProc; class NetProc;
class NetProcTop; class NetProcTop;
@ -70,78 +71,6 @@ struct functor_t;
class NetObj { class NetObj {
public: public:
class Link {
friend void connect(Link&, Link&);
friend class NetObj;
public:
enum DIR { PASSIVE, INPUT, OUTPUT };
Link();
~Link();
// Manipulate the link direction.
void set_dir(DIR d) { dir_ = d; }
DIR get_dir() const { return dir_; }
void cur_link(NetObj*&net, unsigned &pin)
{ net = node_;
pin = pin_;
}
void next_link(NetObj*&net, unsigned&pin);
void next_link(const NetObj*&net, unsigned&pin) const;
Link* next_link();
const Link* next_link() const;
// Remove this link from the set of connected pins. The
// destructor will automatically do this if needed.
void unlink();
// Return true if this link is connected to anything else.
bool is_linked() const;
// Return true if these pins are connected.
bool is_linked(const NetObj::Link&that) const;
// Return true if this link is connected to any pin of r.
bool is_linked(const NetObj&r) const;
bool is_equal(const NetObj::Link&that) const
{ return (node_ == that.node_) && (pin_ == that.pin_); }
// Return information about the object that this link is
// a part of.
const NetObj*get_obj() const;
NetObj*get_obj();
unsigned get_pin() const;
void set_name(const string&, unsigned inst =0);
const string& get_name() const;
unsigned get_inst() const;
private:
// The NetNode manages these. They point back to the
// NetNode so that following the links can get me here.
NetObj *node_;
unsigned pin_;
DIR dir_;
// These members name the pin of the link. If the name
// has width, then the ninst_ member is the index of the
// pin.
string name_;
unsigned inst_;
private:
Link *next_;
Link *prev_;
private: // not implemented
Link(const Link&);
Link& operator= (const Link&);
};
public: public:
explicit NetObj(const string&n, unsigned npins); explicit NetObj(const string&n, unsigned npins);
virtual ~NetObj(); virtual ~NetObj();
@ -188,6 +117,86 @@ class NetObj {
bool mark_; bool mark_;
}; };
class Link {
friend void connect(Link&, Link&);
friend class NetObj;
public:
enum DIR { PASSIVE, INPUT, OUTPUT };
enum strength_t { HIGHZ, WEAK, PULL, STRONG, SUPPLY };
Link();
~Link();
// Manipulate the link direction.
void set_dir(DIR d);
DIR get_dir() const;
void drive0(strength_t);
void drive1(strength_t);
strength_t drive0() const;
strength_t drive1() const;
void cur_link(NetObj*&net, unsigned &pin);
void next_link(NetObj*&net, unsigned&pin);
void next_link(const NetObj*&net, unsigned&pin) const;
Link* next_link();
const Link* next_link() const;
// Remove this link from the set of connected pins. The
// destructor will automatically do this if needed.
void unlink();
// Return true if this link is connected to anything else.
bool is_linked() const;
// Return true if these pins are connected.
bool is_linked(const Link&that) const;
// Return true if this link is connected to any pin of r.
bool is_linked(const NetObj&r) const;
bool is_equal(const Link&that) const
{ return (node_ == that.node_) && (pin_ == that.pin_); }
// Return information about the object that this link is
// a part of.
const NetObj*get_obj() const;
NetObj*get_obj();
unsigned get_pin() const;
void set_name(const string&, unsigned inst =0);
const string& get_name() const;
unsigned get_inst() const;
private:
// The NetNode manages these. They point back to the
// NetNode so that following the links can get me here.
NetObj *node_;
unsigned pin_;
DIR dir_;
strength_t drive0_, drive1_;
// These members name the pin of the link. If the name
// has width, then the ninst_ member is the index of the
// pin.
string name_;
unsigned inst_;
private:
Link *next_;
Link *prev_;
private: // not implemented
Link(const Link&);
Link& operator= (const Link&);
};
/* /*
* A NetNode is a device of some sort, where each pin has a different * A NetNode is a device of some sort, where each pin has a different
* meaning. (i.e. pin(0) is the output to an and gate.) NetNode * meaning. (i.e. pin(0) is the output to an and gate.) NetNode
@ -310,21 +319,21 @@ class NetAddSub : public NetNode {
// operands and results.) // operands and results.)
unsigned width() const; unsigned width() const;
NetObj::Link& pin_Aclr(); Link& pin_Aclr();
NetObj::Link& pin_Add_Sub(); Link& pin_Add_Sub();
NetObj::Link& pin_Clock(); Link& pin_Clock();
NetObj::Link& pin_Cin(); Link& pin_Cin();
NetObj::Link& pin_Cout(); Link& pin_Cout();
NetObj::Link& pin_Overflow(); Link& pin_Overflow();
NetObj::Link& pin_DataA(unsigned idx); Link& pin_DataA(unsigned idx);
NetObj::Link& pin_DataB(unsigned idx); Link& pin_DataB(unsigned idx);
NetObj::Link& pin_Result(unsigned idx); Link& pin_Result(unsigned idx);
const NetObj::Link& pin_Cout() const; const Link& pin_Cout() const;
const NetObj::Link& pin_DataA(unsigned idx) const; const Link& pin_DataA(unsigned idx) const;
const NetObj::Link& pin_DataB(unsigned idx) const; const Link& pin_DataB(unsigned idx) const;
const NetObj::Link& pin_Result(unsigned idx) const; const Link& pin_Result(unsigned idx) const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual void emit_node(ostream&, struct target_t*) const; virtual void emit_node(ostream&, struct target_t*) const;
@ -343,19 +352,19 @@ class NetCLShift : public NetNode {
unsigned width() const; unsigned width() const;
unsigned width_dist() const; unsigned width_dist() const;
NetObj::Link& pin_Direction(); Link& pin_Direction();
NetObj::Link& pin_Underflow(); Link& pin_Underflow();
NetObj::Link& pin_Overflow(); Link& pin_Overflow();
NetObj::Link& pin_Data(unsigned idx); Link& pin_Data(unsigned idx);
NetObj::Link& pin_Result(unsigned idx); Link& pin_Result(unsigned idx);
NetObj::Link& pin_Distance(unsigned idx); Link& pin_Distance(unsigned idx);
const NetObj::Link& pin_Direction() const; const Link& pin_Direction() const;
const NetObj::Link& pin_Underflow() const; const Link& pin_Underflow() const;
const NetObj::Link& pin_Overflow() const; const Link& pin_Overflow() const;
const NetObj::Link& pin_Data(unsigned idx) const; const Link& pin_Data(unsigned idx) const;
const NetObj::Link& pin_Result(unsigned idx) const; const Link& pin_Result(unsigned idx) const;
const NetObj::Link& pin_Distance(unsigned idx) const; const Link& pin_Distance(unsigned idx) const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual void emit_node(ostream&, struct target_t*) const; virtual void emit_node(ostream&, struct target_t*) const;
@ -380,29 +389,29 @@ class NetCompare : public NetNode {
unsigned width() const; unsigned width() const;
NetObj::Link& pin_Aclr(); Link& pin_Aclr();
NetObj::Link& pin_Clock(); Link& pin_Clock();
NetObj::Link& pin_AGB(); Link& pin_AGB();
NetObj::Link& pin_AGEB(); Link& pin_AGEB();
NetObj::Link& pin_AEB(); Link& pin_AEB();
NetObj::Link& pin_ANEB(); Link& pin_ANEB();
NetObj::Link& pin_ALB(); Link& pin_ALB();
NetObj::Link& pin_ALEB(); Link& pin_ALEB();
NetObj::Link& pin_DataA(unsigned idx); Link& pin_DataA(unsigned idx);
NetObj::Link& pin_DataB(unsigned idx); Link& pin_DataB(unsigned idx);
const NetObj::Link& pin_Aclr() const; const Link& pin_Aclr() const;
const NetObj::Link& pin_Clock() const; const Link& pin_Clock() const;
const NetObj::Link& pin_AGB() const; const Link& pin_AGB() const;
const NetObj::Link& pin_AGEB() const; const Link& pin_AGEB() const;
const NetObj::Link& pin_AEB() const; const Link& pin_AEB() const;
const NetObj::Link& pin_ANEB() const; const Link& pin_ANEB() const;
const NetObj::Link& pin_ALB() const; const Link& pin_ALB() const;
const NetObj::Link& pin_ALEB() const; const Link& pin_ALEB() const;
const NetObj::Link& pin_DataA(unsigned idx) const; const Link& pin_DataA(unsigned idx) const;
const NetObj::Link& pin_DataB(unsigned idx) const; const Link& pin_DataB(unsigned idx) const;
virtual void functor_node(Design*, functor_t*); virtual void functor_node(Design*, functor_t*);
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
@ -432,13 +441,13 @@ class NetDivide : public NetNode {
unsigned width_a() const; unsigned width_a() const;
unsigned width_b() const; unsigned width_b() const;
NetObj::Link& pin_DataA(unsigned idx); Link& pin_DataA(unsigned idx);
NetObj::Link& pin_DataB(unsigned idx); Link& pin_DataB(unsigned idx);
NetObj::Link& pin_Result(unsigned idx); Link& pin_Result(unsigned idx);
const NetObj::Link& pin_DataA(unsigned idx) const; const Link& pin_DataA(unsigned idx) const;
const NetObj::Link& pin_DataB(unsigned idx) const; const Link& pin_DataB(unsigned idx) const;
const NetObj::Link& pin_Result(unsigned idx) const; const Link& pin_Result(unsigned idx) const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual void emit_node(ostream&, struct target_t*) const; virtual void emit_node(ostream&, struct target_t*) const;
@ -462,22 +471,22 @@ class NetFF : public NetNode {
unsigned width() const; unsigned width() const;
NetObj::Link& pin_Clock(); Link& pin_Clock();
NetObj::Link& pin_Enable(); Link& pin_Enable();
NetObj::Link& pin_Aload(); Link& pin_Aload();
NetObj::Link& pin_Aset(); Link& pin_Aset();
NetObj::Link& pin_Aclr(); Link& pin_Aclr();
NetObj::Link& pin_Sload(); Link& pin_Sload();
NetObj::Link& pin_Sset(); Link& pin_Sset();
NetObj::Link& pin_Sclr(); Link& pin_Sclr();
NetObj::Link& pin_Data(unsigned); Link& pin_Data(unsigned);
NetObj::Link& pin_Q(unsigned); Link& pin_Q(unsigned);
const NetObj::Link& pin_Clock() const; const Link& pin_Clock() const;
const NetObj::Link& pin_Enable() const; const Link& pin_Enable() const;
const NetObj::Link& pin_Data(unsigned) const; const Link& pin_Data(unsigned) const;
const NetObj::Link& pin_Q(unsigned) const; const Link& pin_Q(unsigned) const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual void emit_node(ostream&, struct target_t*) const; virtual void emit_node(ostream&, struct target_t*) const;
@ -560,21 +569,21 @@ class NetMult : public NetNode {
unsigned width_b() const; // DataB unsigned width_b() const; // DataB
unsigned width_s() const; // Sum (my be 0) unsigned width_s() const; // Sum (my be 0)
NetObj::Link& pin_Aclr(); Link& pin_Aclr();
NetObj::Link& pin_Clock(); Link& pin_Clock();
NetObj::Link& pin_DataA(unsigned idx); Link& pin_DataA(unsigned idx);
NetObj::Link& pin_DataB(unsigned idx); Link& pin_DataB(unsigned idx);
NetObj::Link& pin_Result(unsigned idx); Link& pin_Result(unsigned idx);
NetObj::Link& pin_Sum(unsigned idx); Link& pin_Sum(unsigned idx);
const NetObj::Link& pin_Aclr() const; const Link& pin_Aclr() const;
const NetObj::Link& pin_Clock() const; const Link& pin_Clock() const;
const NetObj::Link& pin_DataA(unsigned idx) const; const Link& pin_DataA(unsigned idx) const;
const NetObj::Link& pin_DataB(unsigned idx) const; const Link& pin_DataB(unsigned idx) const;
const NetObj::Link& pin_Result(unsigned idx) const; const Link& pin_Result(unsigned idx) const;
const NetObj::Link& pin_Sum(unsigned idx) const; const Link& pin_Sum(unsigned idx) const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual void emit_node(ostream&, struct target_t*) const; virtual void emit_node(ostream&, struct target_t*) const;
@ -608,19 +617,19 @@ class NetMux : public NetNode {
unsigned size() const; unsigned size() const;
unsigned sel_width() const; unsigned sel_width() const;
NetObj::Link& pin_Aclr(); Link& pin_Aclr();
NetObj::Link& pin_Clock(); Link& pin_Clock();
NetObj::Link& pin_Result(unsigned); Link& pin_Result(unsigned);
NetObj::Link& pin_Data(unsigned wi, unsigned si); Link& pin_Data(unsigned wi, unsigned si);
NetObj::Link& pin_Sel(unsigned); Link& pin_Sel(unsigned);
const NetObj::Link& pin_Aclr() const; const Link& pin_Aclr() const;
const NetObj::Link& pin_Clock() const; const Link& pin_Clock() const;
const NetObj::Link& pin_Result(unsigned) const; const Link& pin_Result(unsigned) const;
const NetObj::Link& pin_Data(unsigned, unsigned) const; const Link& pin_Data(unsigned, unsigned) const;
const NetObj::Link& pin_Sel(unsigned) const; const Link& pin_Sel(unsigned) const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual void emit_node(ostream&, struct target_t*) const; virtual void emit_node(ostream&, struct target_t*) const;
@ -648,21 +657,21 @@ class NetRamDq : public NetNode {
unsigned size() const; unsigned size() const;
const NetMemory*mem() const; const NetMemory*mem() const;
NetObj::Link& pin_InClock(); Link& pin_InClock();
NetObj::Link& pin_OutClock(); Link& pin_OutClock();
NetObj::Link& pin_WE(); Link& pin_WE();
NetObj::Link& pin_Address(unsigned idx); Link& pin_Address(unsigned idx);
NetObj::Link& pin_Data(unsigned idx); Link& pin_Data(unsigned idx);
NetObj::Link& pin_Q(unsigned idx); Link& pin_Q(unsigned idx);
const NetObj::Link& pin_InClock() const; const Link& pin_InClock() const;
const NetObj::Link& pin_OutClock() const; const Link& pin_OutClock() const;
const NetObj::Link& pin_WE() const; const Link& pin_WE() const;
const NetObj::Link& pin_Address(unsigned idx) const; const Link& pin_Address(unsigned idx) const;
const NetObj::Link& pin_Data(unsigned idx) const; const Link& pin_Data(unsigned idx) const;
const NetObj::Link& pin_Q(unsigned idx) const; const Link& pin_Q(unsigned idx) const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual void emit_node(ostream&, struct target_t*) const; virtual void emit_node(ostream&, struct target_t*) const;
@ -1438,7 +1447,7 @@ class NetForce : public NetProc, public NetNode {
explicit NetForce(const string&n, NetNet*l); explicit NetForce(const string&n, NetNet*l);
~NetForce(); ~NetForce();
const NetObj::Link& lval_pin(unsigned) const; const Link& lval_pin(unsigned) const;
virtual void dump(ostream&, unsigned ind) const; virtual void dump(ostream&, unsigned ind) const;
virtual bool emit_proc(ostream&, struct target_t*) const; virtual bool emit_proc(ostream&, struct target_t*) const;
@ -2194,7 +2203,7 @@ class NetESignal : public NetExpr {
// These methods actually reference the properties of the // These methods actually reference the properties of the
// NetNet object that I point to. // NetNet object that I point to.
unsigned pin_count() const; unsigned pin_count() const;
NetObj::Link& pin(unsigned idx); Link& pin(unsigned idx);
virtual void expr_scan(struct expr_scan_t*) const; virtual void expr_scan(struct expr_scan_t*) const;
virtual void dump(ostream&) const; virtual void dump(ostream&) const;
@ -2460,18 +2469,18 @@ class Design {
/* ======= /* =======
*/ */
inline bool operator == (const NetObj::Link&l, const NetObj::Link&r) inline bool operator == (const Link&l, const Link&r)
{ return l.is_equal(r); } { return l.is_equal(r); }
inline bool operator != (const NetObj::Link&l, const NetObj::Link&r) inline bool operator != (const Link&l, const Link&r)
{ return ! l.is_equal(r); } { return ! l.is_equal(r); }
/* Connect the pins of two nodes together. Either may already be /* Connect the pins of two nodes together. Either may already be
connected to other things, connect is transitive. */ connected to other things, connect is transitive. */
extern void connect(NetObj::Link&, NetObj::Link&); extern void connect(Link&, Link&);
/* Return true if l and r are connected. */ /* Return true if l and r are connected. */
inline bool connected(const NetObj::Link&l, const NetObj::Link&r) inline bool connected(const Link&l, const Link&r)
{ return l.is_linked(r); } { return l.is_linked(r); }
/* Return true if l is fully connected to r. This means, every pin in /* Return true if l is fully connected to r. This means, every pin in
@ -2481,12 +2490,12 @@ extern bool connected(const NetObj&l, const NetObj&r);
/* return the number of links in the ring that are of the specified /* return the number of links in the ring that are of the specified
type. */ type. */
extern unsigned count_inputs(const NetObj::Link&pin); extern unsigned count_inputs(const Link&pin);
extern unsigned count_outputs(const NetObj::Link&pin); extern unsigned count_outputs(const Link&pin);
extern unsigned count_signals(const NetObj::Link&pin); extern unsigned count_signals(const Link&pin);
/* Find the next link that is an output into the nexus. */ /* Find the next link that is an output into the nexus. */
extern NetObj::Link* find_next_output(NetObj::Link*lnk); extern Link* find_next_output(Link*lnk);
/* Find the signal connected to the given node pin. There should /* Find the signal connected to the given node pin. There should
always be exactly one signal. The bidx parameter get filled with always be exactly one signal. The bidx parameter get filled with
@ -2501,6 +2510,14 @@ extern ostream& operator << (ostream&, NetNet::Type);
/* /*
* $Log: netlist.h,v $ * $Log: netlist.h,v $
* Revision 1.136 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.135 2000/05/04 03:37:58 steve * Revision 1.135 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move * Add infrastructure for system functions, move
* $time to that structure and add $random. * $time to that structure and add $random.

14
netmisc.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: netmisc.h,v 1.5 2000/04/20 00:28:03 steve Exp $" #ident "$Id: netmisc.h,v 1.6 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
@ -39,7 +39,7 @@ extern NetNet*pad_to_width(Design*des, const string&p, NetNet*n, unsigned w);
* signals that are not connected together will have a different nexus * signals that are not connected together will have a different nexus
* name. * name.
*/ */
extern string nexus_from_link(const NetObj::Link*lnk); extern string nexus_from_link(const Link*lnk);
/* /*
* Check to see if the link has a constant value driven to it. If * Check to see if the link has a constant value driven to it. If
@ -47,10 +47,18 @@ extern string nexus_from_link(const NetObj::Link*lnk);
* that NetConst object. Also, return the index of the bit in that * that NetConst object. Also, return the index of the bit in that
* constant through the idx parameter. * constant through the idx parameter.
*/ */
extern NetConst* link_const_value(NetObj::Link&pin, unsigned&idx); extern NetConst* link_const_value(Link&pin, unsigned&idx);
/* /*
* $Log: netmisc.h,v $ * $Log: netmisc.h,v $
* Revision 1.6 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.5 2000/04/20 00:28:03 steve * Revision 1.5 2000/04/20 00:28:03 steve
* Catch some simple identity compareoptimizations. * Catch some simple identity compareoptimizations.
* *

14
nexus_from_link.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: nexus_from_link.cc,v 1.2 2000/03/20 17:40:54 steve Exp $" #ident "$Id: nexus_from_link.cc,v 1.3 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include "netmisc.h" # include "netmisc.h"
@ -25,12 +25,12 @@
# include <string> # include <string>
# include <typeinfo> # include <typeinfo>
string nexus_from_link(const NetObj::Link*lnk) string nexus_from_link(const Link*lnk)
{ {
const NetNet*sig = dynamic_cast<const NetNet*>(lnk->get_obj()); const NetNet*sig = dynamic_cast<const NetNet*>(lnk->get_obj());
unsigned pin = lnk->get_pin(); unsigned pin = lnk->get_pin();
for (const NetObj::Link*cur = lnk->next_link() for (const Link*cur = lnk->next_link()
; cur != lnk ; cur = cur->next_link()) { ; cur != lnk ; cur = cur->next_link()) {
const NetNet*cursig = dynamic_cast<const NetNet*>(cur->get_obj()); const NetNet*cursig = dynamic_cast<const NetNet*>(cur->get_obj());
@ -82,6 +82,14 @@ string nexus_from_link(const NetObj::Link*lnk)
/* /*
* $Log: nexus_from_link.cc,v $ * $Log: nexus_from_link.cc,v $
* Revision 1.3 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.2 2000/03/20 17:40:54 steve * Revision 1.2 2000/03/20 17:40:54 steve
* More complete error message about no signal. * More complete error message about no signal.
* *

14
nodangle.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: nodangle.cc,v 1.5 2000/04/28 21:00:29 steve Exp $" #ident "$Id: nodangle.cc,v 1.6 2000/05/07 04:37:56 steve Exp $"
#endif #endif
/* /*
@ -67,8 +67,8 @@ void nodangle_f::signal(Design*des, NetNet*sig)
to every pin of this signal. */ to every pin of this signal. */
unsigned significant_flags = 0; unsigned significant_flags = 0;
for (unsigned idx = 0 ; idx < sig->pin_count() ; idx += 1) { for (unsigned idx = 0 ; idx < sig->pin_count() ; idx += 1) {
NetObj::Link&lnk = sig->pin(idx); Link&lnk = sig->pin(idx);
for (NetObj::Link*cur = lnk.next_link() for (Link*cur = lnk.next_link()
; cur != &lnk ; cur = cur->next_link()) { ; cur != &lnk ; cur = cur->next_link()) {
NetNet*cursig = dynamic_cast<NetNet*>(cur->get_obj()); NetNet*cursig = dynamic_cast<NetNet*>(cur->get_obj());
if (cursig == 0) if (cursig == 0)
@ -94,6 +94,14 @@ void nodangle(Design*des)
/* /*
* $Log: nodangle.cc,v $ * $Log: nodangle.cc,v $
* Revision 1.6 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.5 2000/04/28 21:00:29 steve * Revision 1.5 2000/04/28 21:00:29 steve
* Over agressive signal elimination in constant probadation. * Over agressive signal elimination in constant probadation.
* *

12
propinit.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: propinit.cc,v 1.2 2000/02/23 02:56:55 steve Exp $" #ident "$Id: propinit.cc,v 1.3 2000/05/07 04:37:56 steve Exp $"
#endif #endif
/* /*
@ -61,7 +61,7 @@ static void prop_sequdp_output(NetUDP*udp)
/* Take the output value and write it to all the NetNet pins /* Take the output value and write it to all the NetNet pins
that are connected to the output pin. */ that are connected to the output pin. */
for (NetObj::Link*lnk = udp->pin(0).next_link() for (Link*lnk = udp->pin(0).next_link()
; (*lnk) != udp->pin(0) ; lnk = lnk->next_link()) { ; (*lnk) != udp->pin(0) ; lnk = lnk->next_link()) {
if (NetNet*sig = dynamic_cast<NetNet*>(lnk->get_obj())) if (NetNet*sig = dynamic_cast<NetNet*>(lnk->get_obj()))
@ -81,6 +81,14 @@ void propinit(Design*des)
/* /*
* $Log: propinit.cc,v $ * $Log: propinit.cc,v $
* Revision 1.3 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.2 2000/02/23 02:56:55 steve * Revision 1.2 2000/02/23 02:56:55 steve
* Macintosh compilers do not support ident. * Macintosh compilers do not support ident.
* *

102
t-vvm.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: t-vvm.cc,v 1.143 2000/05/04 03:37:59 steve Exp $" #ident "$Id: t-vvm.cc,v 1.144 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include <iostream> # include <iostream>
@ -108,7 +108,7 @@ class target_vvm : public target_t {
void end_process(ostream&os, const NetProcTop*); void end_process(ostream&os, const NetProcTop*);
private: private:
void emit_init_value_(const NetObj::Link&lnk, verinum::V val); void emit_init_value_(const Link&lnk, verinum::V val);
void emit_gate_outputfun_(const NetNode*, unsigned); void emit_gate_outputfun_(const NetNode*, unsigned);
string defn_gate_outputfun_(ostream&os, const NetNode*, unsigned); string defn_gate_outputfun_(ostream&os, const NetNode*, unsigned);
@ -157,6 +157,51 @@ class target_vvm : public target_t {
unsigned selector_counter; unsigned selector_counter;
}; };
static const char*vvm_val_name(verinum::V val,
Link::strength_t drv0,
Link::strength_t drv1)
{
switch (val) {
case verinum::V0:
switch (drv0) {
case Link::HIGHZ:
return "HiZ";
case Link::WEAK:
return "We0";
case Link::PULL:
return "Pu0";
case Link::STRONG:
return "St0";
case Link::SUPPLY:
return "Su0";
}
break;
case verinum::V1:
switch (drv1) {
case Link::HIGHZ:
return "HiZ";
case Link::WEAK:
return "We1";
case Link::PULL:
return "Pu1";
case Link::STRONG:
return "St1";
case Link::SUPPLY:
return "Su1";
}
break;
case verinum::Vx:
return "StX";
case verinum::Vz:
return "HiZ";
}
return "";
}
target_vvm::target_vvm() target_vvm::target_vvm()
: function_def_flag_(false), init_code_name(0) : function_def_flag_(false), init_code_name(0)
@ -1038,14 +1083,15 @@ string target_vvm::defn_gate_outputfun_(ostream&os,
return ""; return "";
} }
void target_vvm::emit_init_value_(const NetObj::Link&lnk, verinum::V val) void target_vvm::emit_init_value_(const Link&lnk, verinum::V val)
{ {
map<string,bool>written; map<string,bool>written;
const char*val_name = vvm_val_name(val, lnk.drive0(), lnk.drive1());
for (const NetObj::Link*cur = lnk.next_link() for (const Link*cur = lnk.next_link()
; (*cur) != lnk ; cur = cur->next_link()) { ; (*cur) != lnk ; cur = cur->next_link()) {
if (cur->get_dir() == NetObj::Link::OUTPUT) if (cur->get_dir() == Link::OUTPUT)
continue; continue;
if (! dynamic_cast<const NetObj*>(cur->get_obj())) if (! dynamic_cast<const NetObj*>(cur->get_obj()))
@ -1064,22 +1110,7 @@ void target_vvm::emit_init_value_(const NetObj::Link&lnk, verinum::V val)
ostrstream line; ostrstream line;
line << " " << mangle(cur->get_obj()->name()) line << " " << mangle(cur->get_obj()->name())
<< ".init_" << cur->get_name() << "(" << cur->get_inst() << ".init_" << cur->get_name() << "(" << cur->get_inst()
<< ", "; << ", " << val_name << ");" << endl << ends;
switch (val) {
case verinum::V0:
line << "St0";
break;
case verinum::V1:
line << "St1";
break;
case verinum::Vx:
line << "StX";
break;
case verinum::Vz:
line << "HiZ";
break;
}
line << ");" << endl << ends;
// Check to see if the line has already been // Check to see if the line has already been
@ -1757,8 +1788,29 @@ void target_vvm::net_case_cmp(ostream&os, const NetCaseCmp*gate)
*/ */
void target_vvm::net_const(ostream&os, const NetConst*gate) void target_vvm::net_const(ostream&os, const NetConst*gate)
{ {
const string mname = mangle(gate->name());
os << "static vvm_nexus::drive_t " << mname
<< "[" << gate->pin_count() << "];" << endl;
for (unsigned idx = 0 ; idx < gate->pin_count() ; idx += 1) {
string nexus = nexus_from_link(&gate->pin(idx));
unsigned ncode = nexus_wire_map[nexus];
const char*val_str = vvm_val_name(gate->value(idx),
gate->pin(idx).drive0(),
gate->pin(idx).drive1());
init_code << " nexus_wire_table["<<ncode<<"].connect(&"
<< mname << "["<<idx<<"]);" << endl;
start_code << " " << mname << "["<<idx<<"].set_value("
<< val_str << ");" << endl;
}
#if 0
for (unsigned idx = 0 ; idx < gate->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < gate->pin_count() ; idx += 1)
emit_init_value_(gate->pin(idx), gate->value(idx)); emit_init_value_(gate->pin(idx), gate->value(idx));
#endif
} }
@ -2712,6 +2764,14 @@ extern const struct target tgt_vvm = {
}; };
/* /*
* $Log: t-vvm.cc,v $ * $Log: t-vvm.cc,v $
* Revision 1.144 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.143 2000/05/04 03:37:59 steve * Revision 1.143 2000/05/04 03:37:59 steve
* Add infrastructure for system functions, move * Add infrastructure for system functions, move
* $time to that structure and add $random. * $time to that structure and add $random.

28
t-xnf.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: t-xnf.cc,v 1.26 2000/04/23 23:03:13 steve Exp $" #ident "$Id: t-xnf.cc,v 1.27 2000/05/07 04:37:56 steve Exp $"
#endif #endif
/* XNF BACKEND /* XNF BACKEND
@ -99,9 +99,9 @@ class target_xnf : public target_t {
private: private:
static string mangle(const string&); static string mangle(const string&);
static string choose_sig_name(const NetObj::Link*lnk); static string choose_sig_name(const Link*lnk);
static void draw_pin(ostream&os, const string&name, static void draw_pin(ostream&os, const string&name,
const NetObj::Link&lnk); const Link&lnk);
static void draw_sym_with_lcaname(ostream&os, string lca, static void draw_sym_with_lcaname(ostream&os, string lca,
const NetNode*net); const NetNode*net);
static void draw_xor(ostream&os, const NetAddSub*, unsigned idx); static void draw_xor(ostream&os, const NetAddSub*, unsigned idx);
@ -137,13 +137,13 @@ string target_xnf::mangle(const string&name)
* nexus to decide which name to use if there are lots of attached * nexus to decide which name to use if there are lots of attached
* signals. * signals.
*/ */
string target_xnf::choose_sig_name(const NetObj::Link*lnk) string target_xnf::choose_sig_name(const Link*lnk)
{ {
assert(lnk->is_linked()); assert(lnk->is_linked());
const NetNet*sig = dynamic_cast<const NetNet*>(lnk->get_obj()); const NetNet*sig = dynamic_cast<const NetNet*>(lnk->get_obj());
unsigned pin = lnk->get_pin(); unsigned pin = lnk->get_pin();
for (const NetObj::Link*cur = lnk->next_link() for (const Link*cur = lnk->next_link()
; cur != lnk ; cur = cur->next_link()) { ; cur != lnk ; cur = cur->next_link()) {
const NetNet*cursig = dynamic_cast<const NetNet*>(cur->get_obj()); const NetNet*cursig = dynamic_cast<const NetNet*>(cur->get_obj());
@ -186,7 +186,7 @@ string target_xnf::choose_sig_name(const NetObj::Link*lnk)
} }
void target_xnf::draw_pin(ostream&os, const string&name, void target_xnf::draw_pin(ostream&os, const string&name,
const NetObj::Link&lnk) const Link&lnk)
{ {
bool inv = false; bool inv = false;
string use_name = name; string use_name = name;
@ -197,11 +197,11 @@ void target_xnf::draw_pin(ostream&os, const string&name,
char type; char type;
switch (lnk.get_dir()) { switch (lnk.get_dir()) {
case NetObj::Link::INPUT: case Link::INPUT:
case NetObj::Link::PASSIVE: case Link::PASSIVE:
type = 'I'; type = 'I';
break; break;
case NetObj::Link::OUTPUT: case Link::OUTPUT:
type = 'O'; type = 'O';
break; break;
} }
@ -757,7 +757,7 @@ void target_xnf::net_const(ostream&os, const NetConst*c)
for (unsigned idx = 0 ; idx < c->pin_count() ; idx += 1) { for (unsigned idx = 0 ; idx < c->pin_count() ; idx += 1) {
verinum::V v=c->value(idx); verinum::V v=c->value(idx);
assert(v==verinum::V0 || v==verinum::V1); assert(v==verinum::V0 || v==verinum::V1);
const NetObj::Link& lnk = c->pin(idx); const Link& lnk = c->pin(idx);
// Code parallels draw_pin above, some smart c++ guru should // Code parallels draw_pin above, some smart c++ guru should
// find a way to make a method out of this. // find a way to make a method out of this.
unsigned cpin; unsigned cpin;
@ -887,6 +887,14 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj };
/* /*
* $Log: t-xnf.cc,v $ * $Log: t-xnf.cc,v $
* Revision 1.27 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.26 2000/04/23 23:03:13 steve * Revision 1.26 2000/04/23 23:03:13 steve
* automatically generate macro interface code. * automatically generate macro interface code.
* *

43
vvm/vpi_bit.c
View File

@ -17,13 +17,18 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: vpi_bit.c,v 1.2 2000/03/22 05:16:38 steve Exp $" #ident "$Id: vpi_bit.c,v 1.3 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include "vpi_priv.h" # include "vpi_priv.h"
# include <stdio.h> # include <stdio.h>
#define UNAMBIG(v) (((v)&0x0f) == ((v)>>4)) /*
* A signal value is unambiguous if the top 4 bits and the bottom 4
* bits are identical. This means that the VSSSvsss bits of the 8bit
* value have V==v and SSS==sss.
*/
#define UNAMBIG(v) (((v)&0x0f) == (((v)>>4)&0x0f))
# define STREN1(v) ( ((v)&0x80)? ((v)&0xf0) : (0x70 - ((v)&0xf0)) ) # define STREN1(v) ( ((v)&0x80)? ((v)&0xf0) : (0x70 - ((v)&0xf0)) )
@ -48,14 +53,28 @@ vpip_bit_t vpip_bits_resolve(const vpip_bit_t*bits, unsigned nbits)
if (UNAMBIG(res) && UNAMBIG(bits[idx])) { if (UNAMBIG(res) && UNAMBIG(bits[idx])) {
/* If both signals are unambiguous, simply choose /* If both signals are unambiguous, simply choose
the stronger. */ the stronger. If they have the same strength
but different values, then this becomes
ambiguous. */
if ((bits[idx]&0x77) > (res&0x77)) if (bits[idx] == res) {
/* values are equal. do nothing. */
} else if ((bits[idx]&0x07) > (res&0x07)) {
/* New value is stronger. Take it. */
res = bits[idx]; res = bits[idx];
else if (bits[idx]*0x77 == (res&0x77))
res = (res&0xf0) + (bits[idx]&0x0f); } else if ((bits[idx]&0x77) == (res&0x77)) {
else
; /* Strengths are the same. Make value ambiguous. */
res = (res&0x70) | (bits[idx]&0x07) | 0x80;
} else {
/* Must be res is the stronger one. */
}
} else if (UNAMBIG(res) || UNAMBIG(bits[idx])) { } else if (UNAMBIG(res) || UNAMBIG(bits[idx])) {
@ -106,6 +125,14 @@ vpip_bit_t vpip_bits_resolve(const vpip_bit_t*bits, unsigned nbits)
/* /*
* $Log: vpi_bit.c,v $ * $Log: vpi_bit.c,v $
* Revision 1.3 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.2 2000/03/22 05:16:38 steve * Revision 1.2 2000/03/22 05:16:38 steve
* Integrate drive resolution function. * Integrate drive resolution function.
* *

22
vvm/vpi_priv.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: vpi_priv.h,v 1.16 2000/05/04 03:37:59 steve Exp $" #ident "$Id: vpi_priv.h,v 1.17 2000/05/07 04:37:56 steve Exp $"
#endif #endif
/* /*
@ -70,8 +70,20 @@ struct __vpirt;
*/ */
typedef unsigned char vpip_bit_t; typedef unsigned char vpip_bit_t;
# define Su1 0xff
# define St1 0xee # define St1 0xee
# define Pu1 0xdd
# define La1 0xcc
# define We1 0xbb
# define Me1 0xaa
# define Sm1 0x99
# define Su0 0x77
# define St0 0x66 # define St0 0x66
# define Pu0 0x55
# define La0 0x44
# define We0 0x33
# define Me0 0x22
# define Sm0 0x11
# define StX 0xe6 # define StX 0xe6
# define HiZ 0x08 # define HiZ 0x08
@ -354,6 +366,14 @@ extern int vpip_finished();
/* /*
* $Log: vpi_priv.h,v $ * $Log: vpi_priv.h,v $
* Revision 1.17 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.16 2000/05/04 03:37:59 steve * Revision 1.16 2000/05/04 03:37:59 steve
* Add infrastructure for system functions, move * Add infrastructure for system functions, move
* $time to that structure and add $random. * $time to that structure and add $random.

16
xnfio.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: xnfio.cc,v 1.13 2000/05/02 00:58:12 steve Exp $" #ident "$Id: xnfio.cc,v 1.14 2000/05/07 04:37:56 steve Exp $"
#endif #endif
# include "functor.h" # include "functor.h"
@ -70,7 +70,7 @@ static NetLogic* make_obuf(Design*des, NetNet*net)
/* Look for an existing OBUF connected to this signal. If it /* Look for an existing OBUF connected to this signal. If it
is there, then no need to add one. */ is there, then no need to add one. */
for (NetObj::Link*idx = net->pin(0).next_link() for (Link*idx = net->pin(0).next_link()
; *idx != net->pin(0) ; idx = idx->next_link()) { ; *idx != net->pin(0) ; idx = idx->next_link()) {
NetLogic*tmp; NetLogic*tmp;
if ((tmp = dynamic_cast<NetLogic*>(idx->get_obj())) == 0) if ((tmp = dynamic_cast<NetLogic*>(idx->get_obj())) == 0)
@ -161,7 +161,7 @@ static void absorb_OFF(Design*des, NetLogic*buf)
if (buf->type() != NetLogic::BUF) if (buf->type() != NetLogic::BUF)
return; return;
NetObj::Link*drv = find_next_output(&buf->pin(1)); Link*drv = find_next_output(&buf->pin(1));
assert(drv); assert(drv);
/* Make sure the device is a FF with width 1. */ /* Make sure the device is a FF with width 1. */
@ -211,7 +211,7 @@ static void make_ibuf(Design*des, NetNet*net)
/* Look for an existing BUF connected to this signal and /* Look for an existing BUF connected to this signal and
suitably connected that I can use it as an IBUF. */ suitably connected that I can use it as an IBUF. */
for (NetObj::Link*idx = net->pin(0).next_link() for (Link*idx = net->pin(0).next_link()
; *idx != net->pin(0) ; idx = idx->next_link()) { ; *idx != net->pin(0) ; idx = idx->next_link()) {
NetLogic*tmp; NetLogic*tmp;
if ((tmp = dynamic_cast<NetLogic*>(idx->get_obj())) == 0) if ((tmp = dynamic_cast<NetLogic*>(idx->get_obj())) == 0)
@ -356,6 +356,14 @@ void xnfio(Design*des)
/* /*
* $Log: xnfio.cc,v $ * $Log: xnfio.cc,v $
* Revision 1.14 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.13 2000/05/02 00:58:12 steve * Revision 1.13 2000/05/02 00:58:12 steve
* Move signal tables to the NetScope class. * Move signal tables to the NetScope class.
* *