Spelling fixes

All fixes are in comments, except for one error message (was "iternal error")

Makefile.in

@@ -30,7 +30,7 @@ SHELL = /bin/sh
 # The "suffix" is used as an installation suffix. It modifies certain
 # key install paths/files such that a build and install of Icarus Verilog
 # with the same $(prefix) but a different $(suffix) will not interfere.
-# The normal configuratin leaves suffix empty
+# The normal configuration leaves suffix empty
 suffix = @install_suffix@
 
 prefix = @prefix@

driver/main.c

@@ -169,8 +169,8 @@ typedef struct t_command_file {
 p_command_file cmd_file_head = NULL;  /* The FIFO head */
 p_command_file cmd_file_tail = NULL;  /* The FIFO tail */
 
-/* Temprarily store parameter definition from command line and
+/* Temporarily store parameter definition from command line and
- * parse it after we have delt with command file
+ * parse it after we have dealt with command file
  */
 static const char** defparm_base = 0;
 static int defparm_size = 0;
@@ -1105,7 +1105,7 @@ int main(int argc, char **argv)
 
 	/* If we are planning on opening a dependencies file, then
 	   open and truncate it here. The other phases of compilation
-	   will append to the file, so this is necessray to make sure
+	   will append to the file, so this is necessary to make sure
 	   it starts out empty. */
       if (depfile) {
 	    FILE*fd = fopen(depfile, "w");

elab_expr.cc

@@ -729,7 +729,7 @@ NetExpr* PEBinary::elaborate_expr_base_rshift_(Design*des,
 	    return tmp;
       }
 
-	// Falback, handle the general case.
+	// Fallback, handle the general case.
       if (expr_wid > 0)
 	    lp = pad_to_width(lp, expr_wid, *this);
       tmp = new NetEBShift(op_, lp, rp);
@@ -3494,7 +3494,7 @@ NetExpr*PETernary::elaborate_expr(Design*des, NetScope*scope,
 	// evaluation of ternary expressions, but it doesn't disallow
 	// it. The disadvantage of doing this is that semantic errors
 	// in the unused clause will be missed, but people don't seem
-	// to mind, and do apreciate the optimization available here.
+	// to mind, and do appreciate the optimization available here.
       if (NetEConst*tmp = dynamic_cast<NetEConst*> (con)) {
 	    verinum cval = tmp->value();
 	    ivl_assert(*this, cval.len()==1);

expr_synth.cc

@@ -907,7 +907,7 @@ NetNet* NetEUnary::synthesize(Design*des, NetScope*scope, NetExpr*root)
 	    return sig;
       }
 
-      cerr << get_fileline() << ": iternal error: "
+      cerr << get_fileline() << ": internal error: "
 	   << "NetEUnary::synthesize cannot handle op_=" << op_ << endl;
       des->errors += 1;
       return expr_->synthesize(des, scope, root);

ivl_target.h

@@ -607,7 +607,7 @@ extern double      ivl_const_real(ivl_net_const_t net);
  *
  * The discipline domain will not be IVL_DIS_NONE. The "none" domain
  * is a place-holder internally for incomplete parsing, and is also
- * available for code generaters to use.
+ * available for code generators to use.
  */
 extern const char*ivl_discipline_name(ivl_discipline_t net);
 extern ivl_dis_domain_t ivl_discipline_domain(ivl_discipline_t net);
@@ -1696,7 +1696,7 @@ extern int          ivl_scope_time_units(ivl_scope_t net);
  *
  * ivl_signal_discipline
  *    If the signal has been declared with a domain (Verilog-AMS) then
- *    this function wil return a non-nil ivl_discipline_t.
+ *    this function will return a non-nil ivl_discipline_t.
  *
  * ivl_signal_msb
  * ivl_signal_lsb

lexor.lex

@@ -1179,7 +1179,7 @@ static void process_ucdrive(const char*txt)
       cp += strspn(cp, " \t");
       if (strncmp(cp, "//", 2) != 0 &&
           (size_t)(cp-yytext) != strlen(yytext)) {
-	    VLerror(yylloc, "Invalid `unconnected_dirve directive (extra "
+	    VLerror(yylloc, "Invalid `unconnected_drive directive (extra "
 	                    "garbage after precision).");
 	    return;
       }

netlist.h

@@ -1829,7 +1829,7 @@ class NetPartSelect  : public NetNode {
  * that makes sense for the technology.
  *
  * A NetBUFZ is transparent if strengths are passed through it without
- * change. A NetBUFZ is non-transparent if values other then HiZ are
+ * change. A NetBUFZ is non-transparent if values other than HiZ are
  * converted to the strength of the output.
  */
 class NetBUFZ  : public NetNode {

parse_misc.h

@@ -78,7 +78,7 @@ extern bool have_timeunit_decl;
 extern bool have_timeprec_decl;
 
 /*
- * Export there functions because we have to generate PENumber class
+ * Export these functions because we have to generate PENumber class
  * in pform.cc for user defparam definition from command file.
  */
 extern verinum*make_unsized_dec(const char*txt);

pform.cc

@@ -65,7 +65,7 @@ void parm_to_defparam_list(const string&param)
 
     // Resolve hierarchical name for defparam. Remember
     // to deal with bit select for generate scopes. Bit
-    // select expression should be constant interger.
+    // select expression should be constant integer.
     pform_name_t name;
     char *nkey = key;
     char *ptr = strchr(key, '.');
@@ -144,7 +144,7 @@ void parm_to_defparam_list(const string&param)
         char *num = strchr(value, '\'');
         if (num != 0) {
             verinum *val;
-            // BASED_NUMBER, somthing like - scope.parameter='b11
+            // BASED_NUMBER, something like - scope.parameter='b11
             // make sure to check 'h' first because 'b'&'d' may be included
             // in hex format
             if (strchr(num, 'h') || strchr(num, 'H'))

tgt-vhdl/expr.cc

@@ -477,7 +477,7 @@ static vhdl_expr *translate_select(ivl_expr_t e)
                                     new vhdl_type(*from->get_type()));
       }
       else if (from_var_ref->get_type()->get_name() != VHDL_TYPE_STD_LOGIC) {
-         // We can use the more idomatic VHDL slice notation on a
+         // We can use the more idiomatic VHDL slice notation on a
          // single variable reference
          vhdl_type integer(VHDL_TYPE_INTEGER);
          from_var_ref->set_slice(base->cast(&integer), ivl_expr_width(e) - 1);

tgt-vhdl/stmt.cc

@@ -747,7 +747,7 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container,
    bool is_top_level = container == proc->get_container()
       && container->empty();
 
-   // See if this can be implemented in a more idomatic way before we
+   // See if this can be implemented in a more idiomatic way before we
    // fall back on the generic translation
    if (is_top_level && draw_synthesisable_wait(proc, container, stmt))
       return 0;

tgt-vhdl/vhdl_syntax.hh

@@ -571,7 +571,7 @@ public:
    enum assign_type_t { ASSIGN_BLOCK, ASSIGN_NONBLOCK, ASSIGN_CONST };
 
    // Get the sort of assignment statement to generate for
-   // assignemnts to this declaration
+   // assignments to this declaration
    // For some sorts of declarations it doesn't make sense
    // to assign to it so calling assignment_type just raises
    // an assertion failure
@@ -768,7 +768,7 @@ protected:
 
    // If this is true then the body contains a `wait' statement
    // embedded in it somewhere
-   // If this is the case then we can't use a sensitvity list for
+   // If this is the case then we can't use a sensitivity list for
    // the process
    bool contains_wait_stmt_;
 };

tgt-vvp/eval_expr.c

@@ -1942,7 +1942,7 @@ static struct vector_info draw_number_expr(ivl_expr_t expr, unsigned wid)
 /*
  * This little helper function generates the instructions to pad a
  * vector in place. It is assumed that the calling function has set up
- * the first sub_sidth bits of the dest vector, and the signed_flag is
+ * the first sub_width bits of the dest vector, and the signed_flag is
  * true if the extension is to be signed.
  */
 static void pad_in_place(struct vector_info dest, unsigned sub_width, int signed_flag)

tgt-vvp/eval_real.c

@@ -166,7 +166,7 @@ static int draw_number_real(ivl_expr_t expr)
 	/* If this is a negative number, then arrange for the 2's
 	   complement to be calculated as we scan through the
 	   value. Real values are sign-magnitude, and this negation
-	   gets us a magnitide. */
+	   gets us a magnitude. */
 
       int negate = 0;
       int carry = 0;

vvp/dff.h

@@ -30,7 +30,7 @@
  *
  *   port-0:  D input
  *   port-1:  Clock input
- *   port-2:  Clock Enagle input
+ *   port-2:  Clock Enable input
  *   port-3:  Asynchronous D input.
  */
 class vvp_dff  : public vvp_net_fun_t {

vvp/opcodes.txt

@@ -373,7 +373,7 @@ register to read the repetition count from (signed or unsigned).
 %evctl/i sets the repetition to an immediate unsigned value.
 
 %evctl/c clears the event control information. This is needed if a
-%assign/e may be skiped since the %assign/e statements clear the
+%assign/e may be skipped since the %assign/e statements clear the
 event control information and the other %evctl statements assert
 that this information has been cleared. You can get an assert if
 this information is not managed correctly.

vvp/vthread.cc

@@ -972,7 +972,7 @@ bool of_ASSIGN_V0(vthread_t thr, vvp_code_t cp)
       vvp_net_ptr_t ptr (cp->net, 0);
       if (bit >= 4) {
 	      // If the vector is not a synthetic one, then have the
-	      // scheduler pluck it direcly out of my vector space.
+	      // scheduler pluck it directly out of my vector space.
 	    schedule_assign_plucked_vector(ptr, delay, thr->bits4, bit, wid);
       } else {
 	    vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
@@ -2078,7 +2078,7 @@ static unsigned long* divide_bits(unsigned long*ap, unsigned long*bp, unsigned w
 					 ap[cur_ptr+btop+1]);
 	    }
 
-	      // cur_res is a guestimate of the result this far. It
+	      // cur_res is a guesstimate of the result this far. It
 	      // may be 1 too big. (But it will also be >0) Try it,
 	      // and if the difference comes out negative, then adjust.
 

vvp/vvp_island.cc

@@ -291,7 +291,7 @@ vvp_island* compile_find_island(const char*island)
  *
  * The <src> is a label in the domain outside the island, and the
  * <label> is in the domain inside the island. Since this port is
- * bi-directional, the <label> is also avaliable in the domain outside
+ * bi-directional, the <label> is also available in the domain outside
  * the island. The outside should use the <label> to access the nexus
  * that this port represents, because the island will resolve internal
  * drivers with the external driver and make the output available on

vvp/vvp_net.cc

@@ -1212,7 +1212,7 @@ void vvp_vector4_t::mov(unsigned dst, unsigned src, unsigned cnt)
 
 		    // Here we know that either the source or
 		    // destination is unaligned, and also we know that
-		    // the count is less then a full word.
+		    // the count is less than a full word.
 		  unsigned long vmask = (1UL << trans) - 1;
 		  unsigned long tmp;
 

vvp/vvp_net.h

@@ -914,7 +914,7 @@ inline bool vvp_vector8_t::eeq(const vvp_vector8_t&that) const
 	    return true;
 
       if (size_ <= sizeof val_)
-	      // This is equivilent to memcmp(val_, that.val_, sizeof val_)==0
+	      // This is equivalent to memcmp(val_, that.val_, sizeof val_)==0
 	    return ptr_ == that.ptr_;
       else
 	    return memcmp(ptr_, that.ptr_, size_) == 0;
@@ -1163,7 +1163,7 @@ class vvp_net_fil_t  : public vvp_vpi_callback {
 	// bit value. If bits were changed by the force mask, then the
 	// method returns REPL and the caller should propagate the rep
 	// value instead. If the function returns STOP, then all the
-	// output bits are filtered by the force mask ans there is
+	// output bits are filtered by the force mask and there is
 	// nothing to propagate.
       virtual prop_t filter_vec4(const vvp_vector4_t&bit, vvp_vector4_t&rep,
 				 unsigned base, unsigned vwid);
@@ -1184,7 +1184,7 @@ class vvp_net_fil_t  : public vvp_vpi_callback {
       virtual unsigned filter_size() const =0;
 
     public:
-	// Suport for force methods. These are calloed by the
+	// Support for force methods. These are called by the
 	// vvp_net_t::force_* methods to set the force value and mask
 	// for the filter.
       virtual void force_fil_vec4(const vvp_vector4_t&val, vvp_vector2_t mask) =0;
@@ -1227,7 +1227,7 @@ class vvp_net_fil_t  : public vvp_vpi_callback {
 
 	// These templates are similar to filter_mask_, but are
 	// idempotent. Then do not trigger callbacks or otherwise
-	// cause any locak changes. These methods are used to test
+	// cause any local changes. These methods are used to test
 	// arbitrary values against the force mask.
       template <class T> prop_t filter_input_mask_(const T&val, const T&force, T&rep) const;
 

vvp/vvp_net_sig.h

@@ -91,7 +91,7 @@ class vvp_fun_signal_base : public vvp_net_fun_t {
 
 /*
  * Variables and wires can have their values accessed, so this base
- * class offers the unified concept of an acessible value.
+ * class offers the unified concept of an accessible value.
  */
 class vvp_signal_value {
     public:
@@ -280,7 +280,7 @@ class vvp_wire_vec4 : public vvp_wire_base {
       vvp_wire_vec4(unsigned wid, vvp_bit4_t init);
 
 	// The main filter behavior for this class. These methods take
-	// the value that the node is driven to, and applies the firce
+	// the value that the node is driven to, and applies the force
 	// filters. In wires, this also saves the driven value, so
 	// that when a force is released, we can revert to the driven value.
       prop_t filter_vec4(const vvp_vector4_t&bit, vvp_vector4_t&rep,