diff --git a/Makefile.in b/Makefile.in index 7a9f120cc..fc291bf98 100644 --- a/Makefile.in +++ b/Makefile.in @@ -30,7 +30,7 @@ SHELL = /bin/sh # The "suffix" is used as an installation suffix. It modifies certain # key install paths/files such that a build and install of Icarus Verilog # with the same $(prefix) but a different $(suffix) will not interfere. -# The normal configuratin leaves suffix empty +# The normal configuration leaves suffix empty suffix = @install_suffix@ prefix = @prefix@ diff --git a/driver/main.c b/driver/main.c index 51a7c5e74..b966235d1 100644 --- a/driver/main.c +++ b/driver/main.c @@ -169,8 +169,8 @@ typedef struct t_command_file { p_command_file cmd_file_head = NULL; /* The FIFO head */ p_command_file cmd_file_tail = NULL; /* The FIFO tail */ -/* Temprarily store parameter definition from command line and - * parse it after we have delt with command file +/* Temporarily store parameter definition from command line and + * parse it after we have dealt with command file */ static const char** defparm_base = 0; static int defparm_size = 0; @@ -1105,7 +1105,7 @@ int main(int argc, char **argv) /* If we are planning on opening a dependencies file, then open and truncate it here. The other phases of compilation - will append to the file, so this is necessray to make sure + will append to the file, so this is necessary to make sure it starts out empty. */ if (depfile) { FILE*fd = fopen(depfile, "w"); diff --git a/elab_expr.cc b/elab_expr.cc index eacaffde2..efe32ed0f 100644 --- a/elab_expr.cc +++ b/elab_expr.cc @@ -729,7 +729,7 @@ NetExpr* PEBinary::elaborate_expr_base_rshift_(Design*des, return tmp; } - // Falback, handle the general case. + // Fallback, handle the general case. if (expr_wid > 0) lp = pad_to_width(lp, expr_wid, *this); tmp = new NetEBShift(op_, lp, rp); @@ -3494,7 +3494,7 @@ NetExpr*PETernary::elaborate_expr(Design*des, NetScope*scope, // evaluation of ternary expressions, but it doesn't disallow // it. The disadvantage of doing this is that semantic errors // in the unused clause will be missed, but people don't seem - // to mind, and do apreciate the optimization available here. + // to mind, and do appreciate the optimization available here. if (NetEConst*tmp = dynamic_cast (con)) { verinum cval = tmp->value(); ivl_assert(*this, cval.len()==1); diff --git a/expr_synth.cc b/expr_synth.cc index c279364ae..c4d0c39c9 100644 --- a/expr_synth.cc +++ b/expr_synth.cc @@ -907,7 +907,7 @@ NetNet* NetEUnary::synthesize(Design*des, NetScope*scope, NetExpr*root) return sig; } - cerr << get_fileline() << ": iternal error: " + cerr << get_fileline() << ": internal error: " << "NetEUnary::synthesize cannot handle op_=" << op_ << endl; des->errors += 1; return expr_->synthesize(des, scope, root); diff --git a/ivl_target.h b/ivl_target.h index 35946e776..c63531697 100644 --- a/ivl_target.h +++ b/ivl_target.h @@ -607,7 +607,7 @@ extern double ivl_const_real(ivl_net_const_t net); * * The discipline domain will not be IVL_DIS_NONE. The "none" domain * is a place-holder internally for incomplete parsing, and is also - * available for code generaters to use. + * available for code generators to use. */ extern const char*ivl_discipline_name(ivl_discipline_t net); extern ivl_dis_domain_t ivl_discipline_domain(ivl_discipline_t net); @@ -1696,7 +1696,7 @@ extern int ivl_scope_time_units(ivl_scope_t net); * * ivl_signal_discipline * If the signal has been declared with a domain (Verilog-AMS) then - * this function wil return a non-nil ivl_discipline_t. + * this function will return a non-nil ivl_discipline_t. * * ivl_signal_msb * ivl_signal_lsb diff --git a/lexor.lex b/lexor.lex index 00e8dc96c..ff96863c4 100644 --- a/lexor.lex +++ b/lexor.lex @@ -1179,7 +1179,7 @@ static void process_ucdrive(const char*txt) cp += strspn(cp, " \t"); if (strncmp(cp, "//", 2) != 0 && (size_t)(cp-yytext) != strlen(yytext)) { - VLerror(yylloc, "Invalid `unconnected_dirve directive (extra " + VLerror(yylloc, "Invalid `unconnected_drive directive (extra " "garbage after precision)."); return; } diff --git a/netlist.h b/netlist.h index 6c25220eb..e2c165d92 100644 --- a/netlist.h +++ b/netlist.h @@ -1829,7 +1829,7 @@ class NetPartSelect : public NetNode { * that makes sense for the technology. * * A NetBUFZ is transparent if strengths are passed through it without - * change. A NetBUFZ is non-transparent if values other then HiZ are + * change. A NetBUFZ is non-transparent if values other than HiZ are * converted to the strength of the output. */ class NetBUFZ : public NetNode { diff --git a/parse_misc.h b/parse_misc.h index 40efbfffa..f3b5dfc9b 100644 --- a/parse_misc.h +++ b/parse_misc.h @@ -78,7 +78,7 @@ extern bool have_timeunit_decl; extern bool have_timeprec_decl; /* - * Export there functions because we have to generate PENumber class + * Export these functions because we have to generate PENumber class * in pform.cc for user defparam definition from command file. */ extern verinum*make_unsized_dec(const char*txt); diff --git a/pform.cc b/pform.cc index 230843bd2..7b5566018 100644 --- a/pform.cc +++ b/pform.cc @@ -65,7 +65,7 @@ void parm_to_defparam_list(const string¶m) // Resolve hierarchical name for defparam. Remember // to deal with bit select for generate scopes. Bit - // select expression should be constant interger. + // select expression should be constant integer. pform_name_t name; char *nkey = key; char *ptr = strchr(key, '.'); @@ -144,7 +144,7 @@ void parm_to_defparam_list(const string¶m) char *num = strchr(value, '\''); if (num != 0) { verinum *val; - // BASED_NUMBER, somthing like - scope.parameter='b11 + // BASED_NUMBER, something like - scope.parameter='b11 // make sure to check 'h' first because 'b'&'d' may be included // in hex format if (strchr(num, 'h') || strchr(num, 'H')) diff --git a/tgt-vhdl/expr.cc b/tgt-vhdl/expr.cc index 11dd41683..a382fb8f6 100644 --- a/tgt-vhdl/expr.cc +++ b/tgt-vhdl/expr.cc @@ -477,7 +477,7 @@ static vhdl_expr *translate_select(ivl_expr_t e) new vhdl_type(*from->get_type())); } else if (from_var_ref->get_type()->get_name() != VHDL_TYPE_STD_LOGIC) { - // We can use the more idomatic VHDL slice notation on a + // We can use the more idiomatic VHDL slice notation on a // single variable reference vhdl_type integer(VHDL_TYPE_INTEGER); from_var_ref->set_slice(base->cast(&integer), ivl_expr_width(e) - 1); diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc index 77952521e..7d217eb09 100644 --- a/tgt-vhdl/stmt.cc +++ b/tgt-vhdl/stmt.cc @@ -747,7 +747,7 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container, bool is_top_level = container == proc->get_container() && container->empty(); - // See if this can be implemented in a more idomatic way before we + // See if this can be implemented in a more idiomatic way before we // fall back on the generic translation if (is_top_level && draw_synthesisable_wait(proc, container, stmt)) return 0; diff --git a/tgt-vhdl/vhdl_syntax.hh b/tgt-vhdl/vhdl_syntax.hh index 3f1c78719..2d792a6a8 100644 --- a/tgt-vhdl/vhdl_syntax.hh +++ b/tgt-vhdl/vhdl_syntax.hh @@ -571,7 +571,7 @@ public: enum assign_type_t { ASSIGN_BLOCK, ASSIGN_NONBLOCK, ASSIGN_CONST }; // Get the sort of assignment statement to generate for - // assignemnts to this declaration + // assignments to this declaration // For some sorts of declarations it doesn't make sense // to assign to it so calling assignment_type just raises // an assertion failure @@ -768,7 +768,7 @@ protected: // If this is true then the body contains a `wait' statement // embedded in it somewhere - // If this is the case then we can't use a sensitvity list for + // If this is the case then we can't use a sensitivity list for // the process bool contains_wait_stmt_; }; diff --git a/tgt-vvp/eval_expr.c b/tgt-vvp/eval_expr.c index c0ed35ff2..248b3df80 100644 --- a/tgt-vvp/eval_expr.c +++ b/tgt-vvp/eval_expr.c @@ -1942,7 +1942,7 @@ static struct vector_info draw_number_expr(ivl_expr_t expr, unsigned wid) /* * This little helper function generates the instructions to pad a * vector in place. It is assumed that the calling function has set up - * the first sub_sidth bits of the dest vector, and the signed_flag is + * the first sub_width bits of the dest vector, and the signed_flag is * true if the extension is to be signed. */ static void pad_in_place(struct vector_info dest, unsigned sub_width, int signed_flag) diff --git a/tgt-vvp/eval_real.c b/tgt-vvp/eval_real.c index f7813a4d6..b3fc68e71 100644 --- a/tgt-vvp/eval_real.c +++ b/tgt-vvp/eval_real.c @@ -166,7 +166,7 @@ static int draw_number_real(ivl_expr_t expr) /* If this is a negative number, then arrange for the 2's complement to be calculated as we scan through the value. Real values are sign-magnitude, and this negation - gets us a magnitide. */ + gets us a magnitude. */ int negate = 0; int carry = 0; diff --git a/vvp/dff.h b/vvp/dff.h index 2915ee960..3f6372b0d 100644 --- a/vvp/dff.h +++ b/vvp/dff.h @@ -30,7 +30,7 @@ * * port-0: D input * port-1: Clock input - * port-2: Clock Enagle input + * port-2: Clock Enable input * port-3: Asynchronous D input. */ class vvp_dff : public vvp_net_fun_t { diff --git a/vvp/opcodes.txt b/vvp/opcodes.txt index 6a2351fae..7ea27d598 100644 --- a/vvp/opcodes.txt +++ b/vvp/opcodes.txt @@ -373,7 +373,7 @@ register to read the repetition count from (signed or unsigned). %evctl/i sets the repetition to an immediate unsigned value. %evctl/c clears the event control information. This is needed if a -%assign/e may be skiped since the %assign/e statements clear the +%assign/e may be skipped since the %assign/e statements clear the event control information and the other %evctl statements assert that this information has been cleared. You can get an assert if this information is not managed correctly. diff --git a/vvp/vthread.cc b/vvp/vthread.cc index 5bc2326fd..e70a366e2 100644 --- a/vvp/vthread.cc +++ b/vvp/vthread.cc @@ -972,7 +972,7 @@ bool of_ASSIGN_V0(vthread_t thr, vvp_code_t cp) vvp_net_ptr_t ptr (cp->net, 0); if (bit >= 4) { // If the vector is not a synthetic one, then have the - // scheduler pluck it direcly out of my vector space. + // scheduler pluck it directly out of my vector space. schedule_assign_plucked_vector(ptr, delay, thr->bits4, bit, wid); } else { vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid); @@ -2078,7 +2078,7 @@ static unsigned long* divide_bits(unsigned long*ap, unsigned long*bp, unsigned w ap[cur_ptr+btop+1]); } - // cur_res is a guestimate of the result this far. It + // cur_res is a guesstimate of the result this far. It // may be 1 too big. (But it will also be >0) Try it, // and if the difference comes out negative, then adjust. diff --git a/vvp/vvp_island.cc b/vvp/vvp_island.cc index b4166d147..1b79d932e 100644 --- a/vvp/vvp_island.cc +++ b/vvp/vvp_island.cc @@ -291,7 +291,7 @@ vvp_island* compile_find_island(const char*island) * * The is a label in the domain outside the island, and the *