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Fix assertion failure when top level module has array ports. 

Reported by Kustaa Nyholm on iverilog-devel, 2017-10-17.

(cherry picked from commit a8318db21c)
This commit is contained in:
Martin Whitaker 2019-08-03 18:52:49 +01:00
parent a6eb59192e
commit b7b22660e5
1 changed files with 1 additions and 2 deletions
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elaborate.cc
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@ -6411,8 +6411,7 @@ Design* elaborate(list<perm_string>roots)
if (netnet != 0) { if (netnet != 0) {
// Elaboration may actually fail with // Elaboration may actually fail with
// erroneous input source // erroneous input source
ivl_assert(*mport[pin], netnet->pin_count()==1); prt_vector_width += netnet->vector_width() * netnet->pin_count();
prt_vector_width += netnet->vector_width();
ptype = PortType::merged(netnet->port_type(), ptype); ptype = PortType::merged(netnet->port_type(), ptype);
} }
} }