From b7b22660e52fc012d5cc00b5d8703feb9db13178 Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Sat, 3 Aug 2019 18:52:49 +0100
Subject: [PATCH] Fix assertion failure when top level module has array ports.

Reported by Kustaa Nyholm on iverilog-devel, 2017-10-17.

(cherry picked from commit a8318db21ccffa8e41bdf06fb8fa4ae54fbfefba)
---
 elaborate.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/elaborate.cc b/elaborate.cc
index fc922b08c..48af74f4d 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -6411,8 +6411,7 @@ Design* elaborate(list<perm_string>roots)
 			if (netnet != 0) {
 			  // Elaboration may actually fail with
 			  // erroneous input source
-			  ivl_assert(*mport[pin], netnet->pin_count()==1);
-                          prt_vector_width += netnet->vector_width();
+                          prt_vector_width += netnet->vector_width() * netnet->pin_count();
                           ptype = PortType::merged(netnet->port_type(), ptype);
 			}
 		  }