From ac71df5257c1474a11710a5588d7a47dcc6dd119 Mon Sep 17 00:00:00 2001 From: steve Date: Wed, 18 Nov 1998 04:25:22 +0000 Subject: [PATCH] Add -f flags for generic flag key/values. --- README.txt | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ main.cc | 34 +++++++++++++++++++-- netlist.cc | 14 ++++++++- netlist.h | 19 +++++++++++- t-xnf.cc | 23 ++++++++++++-- 5 files changed, 172 insertions(+), 7 deletions(-) create mode 100644 README.txt diff --git a/README.txt b/README.txt new file mode 100644 index 000000000..0b3f34ec5 --- /dev/null +++ b/README.txt @@ -0,0 +1,89 @@ + +INVOKING + +The vl command is the compiler driver, that invokes the parser, +optimization functions and the code generator. + +Usage: vl [-s ] [-o ] [-D] [-F ] [-t ] file + vl -h + +-F + Use this flag to request an optimization function be applied + to the netlist before it is sent to the target output + stage. Any number of -F options may be given, to specify a + variety of processing steps. The steps will be applied in + order, with the output of one uses as the input to the next. + + The function is specified by name. Use the "vl -h" command to + get a list of configured function names. + +-f + Use this flag to set a parameter value. The format of the + assignment is = where key is any string up to the + first '=', and is the rest of the option. If the '=' + is omitted, then the key is assigned the empty string. + + The useful keys are defined by the functions and the target in + use. These assignments are specifically useful for passing + target specific information to the target backend, or + options/parameters to optimization functions, if any are defined. + +-o + Normally, the generated result is sent to standard + output. Use the -o flag to specify an output file for the + generated result. + +-s + Normally, vl will elaborate the only module in the source + file. If there are multiple modules, use this option to select + the module to be used as the top-level module. + +-t + Select the output format for the compiled result. Use the + "vl -h" command to get a list of configured targets. + + +HOW IT WORKS -- STAGES OF PROCESSING + +* Parse + +The verilog compiler starts by parsing the verilog source file. The +output of the parse in a list of Module objects in PFORM. The pform +(see pform.h) is mostly a direct reflection of the compilation +unit. There may be dangling references, and it is not yet clear which +module is the root. + +* Elaboration + +This phase takes the pform and generates a netlist. The driver selects +(by user request or lucky guess) the root module to elaborate, +resolves references and expands the instantiations to form the design +netlist. + +The elaborate() function performs the elaboration. + +* Optimization + +This is actually a collection of processing steps that perform +optimizations that do not depend on the target technology. Examples of +some useful transformations would be, + + - eliminate null effect circuitry, + - combinational reduction + - Constant propogation + +The actual functions performed are specified on the command line by +the -F flags. + +* Code Generation + +This step takes the design netlist and uses it to drive the code +generator. (See target.h.) This may require transforming the +design to suit the technology. + +The emit() method of the Design class performs this step. It runs +through the design elements, calling target functions as need arises +to generate actual output. + +The target code generator to used is given by the -t flag on the +command line. diff --git a/main.cc b/main.cc index 8bb7bbec3..8512cc982 100644 --- a/main.cc +++ b/main.cc @@ -17,13 +17,14 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: main.cc,v 1.4 1998/11/16 05:03:52 steve Exp $" +#ident "$Id: main.cc,v 1.5 1998/11/18 04:25:22 steve Exp $" #endif # include # include # include # include +# include # include # include "pform.h" # include "netlist.h" @@ -35,6 +36,25 @@ const char*vl_file = ""; const char*target = "verilog"; string start_module = ""; +map flags; + +static void parm_to_flagmap(const string&flag) +{ + string key, value; + unsigned off = flag.find('='); + if (off > flag.size()) { + key = flag; + value = ""; + + } else { + key = flag.substr(0, off); + value = flag.substr(off+1); + } + + flags[key] = value; +} + + extern Design* elaborate(const list&modules, const string&root); extern void emit(ostream&o, const Design*, const char*); @@ -72,7 +92,7 @@ int main(int argc, char*argv[]) unsigned flag_errors = 0; queue net_func_queue; - while ((opt = getopt(argc, argv, "DF:ho:s:t:")) != EOF) switch (opt) { + while ((opt = getopt(argc, argv, "DF:f:ho:s:t:")) != EOF) switch (opt) { case 'D': dump_flag = true; break; @@ -81,11 +101,15 @@ int main(int argc, char*argv[]) if (tmp == 0) { cerr << "No such design transform function ``" << optarg << "''." << endl; + flag_errors += 1; break; } net_func_queue.push(tmp); break; } + case 'f': + parm_to_flagmap(optarg); + break; case 'h': help_flag = true; break; @@ -160,6 +184,9 @@ int main(int argc, char*argv[]) return 1; } + des->set_flags(flags); + + while (!net_func_queue.empty()) { net_func func = net_func_queue.front(); net_func_queue.pop(); @@ -192,6 +219,9 @@ int main(int argc, char*argv[]) /* * $Log: main.cc,v $ + * Revision 1.5 1998/11/18 04:25:22 steve + * Add -f flags for generic flag key/values. + * * Revision 1.4 1998/11/16 05:03:52 steve * Add the sigfold function that unlinks excess * signal nodes, and add the XNF target. diff --git a/netlist.cc b/netlist.cc index 72f66bd7e..55dae8f0d 100644 --- a/netlist.cc +++ b/netlist.cc @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: netlist.cc,v 1.6 1998/11/16 05:03:53 steve Exp $" +#ident "$Id: netlist.cc,v 1.7 1998/11/18 04:25:22 steve Exp $" #endif # include @@ -218,6 +218,15 @@ void NetEUnary::set_width(unsigned w) expr_width(w); } +string Design::get_flag(const string&key) const +{ + map::const_iterator tmp = flags_.find(key); + if (tmp == flags_.end()) + return ""; + else + return (*tmp).second; +} + void Design::add_signal(NetNet*net) { assert(net->design_ == 0); @@ -361,6 +370,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*)) /* * $Log: netlist.cc,v $ + * Revision 1.7 1998/11/18 04:25:22 steve + * Add -f flags for generic flag key/values. + * * Revision 1.6 1998/11/16 05:03:53 steve * Add the sigfold function that unlinks excess * signal nodes, and add the XNF target. diff --git a/netlist.h b/netlist.h index 1a854a7f3..a7e5029e7 100644 --- a/netlist.h +++ b/netlist.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: netlist.h,v 1.6 1998/11/16 05:03:53 steve Exp $" +#ident "$Id: netlist.h,v 1.7 1998/11/18 04:25:22 steve Exp $" #endif /* @@ -29,6 +29,7 @@ * processors. */ # include +# include # include "verinum.h" class NetNode; @@ -654,6 +655,17 @@ class Design { public: Design() : signals_(0), nodes_(0), procs_(0) { } + /* The flags are a generic way of accepting command line + parameters/flags and passing them to the processing steps + that deal with the design. The compilation driver sets the + entire flags map after elaboration is done. Subsequent + steps can then use the get_flag() function to get the value + of an interesting key. */ + + void set_flags(const map&f) { flags_ = f; } + + string get_flag(const string&key) const; + // SIGNALS @@ -688,6 +700,8 @@ class Design { // List the processes in the design. NetProcTop*procs_; + map flags_; + private: // not implemented Design(const Design&); Design& operator= (const Design&); @@ -713,6 +727,9 @@ inline ostream& operator << (ostream&o, const NetExpr&exp) /* * $Log: netlist.h,v $ + * Revision 1.7 1998/11/18 04:25:22 steve + * Add -f flags for generic flag key/values. + * * Revision 1.6 1998/11/16 05:03:53 steve * Add the sigfold function that unlinks excess * signal nodes, and add the XNF target. diff --git a/t-xnf.cc b/t-xnf.cc index 78ca8c592..cbd5ef923 100644 --- a/t-xnf.cc +++ b/t-xnf.cc @@ -17,9 +17,23 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: t-xnf.cc,v 1.1 1998/11/16 05:03:53 steve Exp $" +#ident "$Id: t-xnf.cc,v 1.2 1998/11/18 04:25:22 steve Exp $" #endif +/* XNF BACKEND + * This target supports generating Xilinx Netlist Format netlists for + * use by Xilinx tools, and other tools that accepts Xilinx designs. + * + * FLAGS + * The XNF backend uses the following flags from the command line to + * affect the generated file: + * + * part= + * Specify the part type. The part string is written into the + * PART record. Valid types are defined by Xilinx or the + * receiving tools + */ + # include "netlist.h" # include "target.h" @@ -55,11 +69,11 @@ string target_xnf::mangle(const string&name) } -void target_xnf::start_design(ostream&os, const Design*) +void target_xnf::start_design(ostream&os, const Design*des) { os << "LCANET,6" << endl; os << "PROG,verilog,0.0,\"Steve's Verilog\"" << endl; - os << "PART,4000-10" << endl; + os << "PART," << des->get_flag("part") << endl; } void target_xnf::end_design(ostream&os, const Design*) @@ -124,6 +138,9 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj }; /* * $Log: t-xnf.cc,v $ + * Revision 1.2 1998/11/18 04:25:22 steve + * Add -f flags for generic flag key/values. + * * Revision 1.1 1998/11/16 05:03:53 steve * Add the sigfold function that unlinks excess * signal nodes, and add the XNF target.