diff --git a/tgt-vhdl/process.cc b/tgt-vhdl/process.cc
index ce4c6c205..4542469f2 100644
--- a/tgt-vhdl/process.cc
+++ b/tgt-vhdl/process.cc
@@ -40,8 +40,8 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
    const char *type = ivl_process_type(proc) == IVL_PR_INITIAL
       ? "initial" : "always";
    std::ostringstream ss;
-   ss << "Generated from " << type << " process in scope ";
-   ss << ivl_scope_name(scope);
+   ss << "Generated from " << type << " process in ";
+   ss << ivl_scope_tname(scope);
    vhdl_proc->set_comment(ss.str());
 
    // Store it in the entity's architecture
diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc
index 14f764cf9..e0e1a475c 100644
--- a/tgt-vhdl/scope.cc
+++ b/tgt-vhdl/scope.cc
@@ -48,9 +48,7 @@ static vhdl_entity *create_entity_for(ivl_scope_t scope)
 
    // Build a comment to add to the entity/architecture
    std::ostringstream ss;
-   ss << "Generated from " << ivl_scope_name(scope);
-   ss << " (" << ivl_scope_def_file(scope) << ":";
-   ss << ivl_scope_def_lineno(scope) << ")";
+   ss << "Generated from Verilog module " << ivl_scope_tname(scope);
    
    arch->set_comment(ss.str());
    ent->set_comment(ss.str());
@@ -97,10 +95,8 @@ static int draw_module(ivl_scope_t scope, ivl_scope_t parent)
          
          // And an instantiation statement
          const char *inst_name = ivl_scope_basename(scope);
-         vhdl_comp_inst *inst = new vhdl_comp_inst(inst_name, ent->get_name().c_str());
-         std::ostringstream ss;
-         ss << "Generated from " << ivl_scope_name(scope);
-         inst->set_comment(ss.str());
+         vhdl_comp_inst *inst =
+            new vhdl_comp_inst(inst_name, ent->get_name().c_str());
          parent_arch->add_stmt(inst);
       }
       else {
diff --git a/tgt-vhdl/vhdl_element.cc b/tgt-vhdl/vhdl_element.cc
index 6578cb1c0..2cce979c6 100644
--- a/tgt-vhdl/vhdl_element.cc
+++ b/tgt-vhdl/vhdl_element.cc
@@ -208,7 +208,7 @@ void vhdl_process::emit(std::ofstream &of, int level) const
    of << "begin";
    newline(of, level);
    // ...statements...
-   of << "wait;";   // Just to stop the simulation hanging
+   of << "  wait;";   // Just to stop the simulation hanging
    newline(of, level);
    of << "end process;";
    newline(of, level);