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Fix port-list-less declaration-less functions for SystemVerilog 

For functions without a port list in parantheses, declarations are optional in SystemVerilog.
This is true even in IEEE1800-2005, but not in IEEE1364-2005
This commit is contained in:
Purdea Andrei 2020-06-22 23:38:15 +03:00
parent ed7734c795
commit a4d91c9023
1 changed files with 1 additions and 1 deletions
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parse.y
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@ -1411,7 +1411,7 @@ function_declaration /* IEEE1800-2005: A.2.6 */
{ assert(current_function == 0); { assert(current_function == 0);
current_function = pform_push_function_scope(@1, $4, $2); current_function = pform_push_function_scope(@1, $4, $2);
} }
function_item_list statement_or_null_list_opt function_item_list_opt statement_or_null_list_opt
K_endfunction K_endfunction
{ current_function->set_ports($7); { current_function->set_ports($7);
current_function->set_return($3); current_function->set_return($3);