From a4d91c90233b6e7d881398977306036710ebb03c Mon Sep 17 00:00:00 2001
From: Purdea Andrei <andrei@purdea.ro>
Date: Mon, 22 Jun 2020 23:38:15 +0300
Subject: [PATCH] Fix port-list-less declaration-less functions for
 SystemVerilog

For functions without a port list in parantheses, declarations are optional in SystemVerilog.
This is true even in IEEE1800-2005, but not in IEEE1364-2005
---
 parse.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/parse.y b/parse.y
index 470cccd57..6a5c28e98 100644
--- a/parse.y
+++ b/parse.y
@@ -1411,7 +1411,7 @@ function_declaration /* IEEE1800-2005: A.2.6 */
       { assert(current_function == 0);
 	current_function = pform_push_function_scope(@1, $4, $2);
       }
-    function_item_list statement_or_null_list_opt
+    function_item_list_opt statement_or_null_list_opt
     K_endfunction
       { current_function->set_ports($7);
 	current_function->set_return($3);