From a4145534e452f644394b3350551324360b3428b6 Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Thu, 2 Jun 2011 19:11:20 -0700
Subject: [PATCH] Declare vhdl module ports inline, a la ansi-c

Keep the entity/component/module port declarations in the module port
list of the generated code. This clarifies the generated code and
fixes a couple bugs for more complicated types.
---
 vhdlpp/entity_emit.cc | 18 ++----------------
 vhdlpp/vsignal.cc     |  1 +
 vhdlpp/vtype_emit.cc  |  4 ++--
 3 files changed, 5 insertions(+), 18 deletions(-)

diff --git a/vhdlpp/entity_emit.cc b/vhdlpp/entity_emit.cc
index 0a4beb114..ef15ad5e2 100644
--- a/vhdlpp/entity_emit.cc
+++ b/vhdlpp/entity_emit.cc
@@ -62,19 +62,11 @@ int Entity::emit(ostream&out)
 			break;
 		      case PORT_IN:
 			out << "input ";
-			if (decl.msb != decl.lsb)
-			      out << "[" << decl.msb
-				  << ":" << decl.lsb << "] ";
-			out << port->name;
+			decl.emit(out, port->name);
 			break;
 		      case PORT_OUT:
 			out << "output ";
-			if (decl.reg_flag)
-			      out << "reg ";
-			if (decl.msb != decl.lsb)
-			      out << "[" << decl.msb
-				  << ":" << decl.lsb << "] ";
-			out << port->name;
+			decl.emit(out, port->name);
 			break;
 		  }
 	    }
@@ -83,12 +75,6 @@ int Entity::emit(ostream&out)
 
       out << ";" << endl;
 
-      for (map<perm_string,VType::decl_t>::const_iterator cur = declarations_.begin()
-		 ; cur != declarations_.end() ; ++cur) {
-
-	    cur->second.emit(out, cur->first);
-      }
-
       errors += bind_arch_->emit(out, this);
 
       out << "endmodule" << endl;
diff --git a/vhdlpp/vsignal.cc b/vhdlpp/vsignal.cc
index b0c014884..c72211608 100644
--- a/vhdlpp/vsignal.cc
+++ b/vhdlpp/vsignal.cc
@@ -39,5 +39,6 @@ int Signal::emit(ostream&out, Entity*, Architecture*)
       VType::decl_t decl;
       type_->elaborate(decl);
       errors += decl.emit(out, name_);
+      out << ";" << endl;
       return errors;
 }
diff --git a/vhdlpp/vtype_emit.cc b/vhdlpp/vtype_emit.cc
index 482b523db..b5b84cc7c 100644
--- a/vhdlpp/vtype_emit.cc
+++ b/vhdlpp/vtype_emit.cc
@@ -39,7 +39,7 @@ int VType::decl_t::emit(ostream&out, perm_string name) const
 		  out << "signed ";
 	    if (msb != lsb)
 		  out << "[" << msb << ":" << lsb << "] ";
-	    out << name << ";" << endl;
+	    out << name;
 	    break;
 	  case VType::VBOOL:
 	    out << wire << " bool ";
@@ -47,7 +47,7 @@ int VType::decl_t::emit(ostream&out, perm_string name) const
 		  out << "signed ";
 	    if (msb != lsb)
 		  out << "[" << msb << ":" << lsb << "] ";
-	    out << name << ";" << endl;
+	    out << name;
 	    break;
       }