From a19a07254b0ad3683b5aaa6bc46f71d22a096195 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 13 Sep 2022 10:09:18 +0200 Subject: [PATCH] Support default port values in port declarations lists Both Verilog (2005) and SystemVerilog support default port values for variable output ports. SystemVerilog also supports default port values for input ports. For port declaration lists it is possible to specify the default value for port identifier. E.g. ``` module M ( input integer x, y = 1, output integer z, w = 2 ) ... ``` Currently the parser only supports specifying the default value for the first identifier in the list. Extend the parser to also allow to specify the default value for identifiers in the list. Signed-off-by: Lars-Peter Clausen --- parse.y | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/parse.y b/parse.y index f1b12a4d4..52c67ab34 100644 --- a/parse.y +++ b/parse.y @@ -4332,13 +4332,29 @@ list_of_port_declarations tmp->push_back($3); $$ = tmp; } - | list_of_port_declarations ',' IDENTIFIER + | list_of_port_declarations ',' IDENTIFIER initializer_opt { Module::port_t*ptmp; perm_string name = lex_strings.make($3); ptmp = pform_module_port_reference(@3, name); std::vector*tmp = $1; tmp->push_back(ptmp); + if ($4) { + switch (port_declaration_context.port_type) { + case NetNet::PINOUT: + yyerror(@4, "error: Default port value not allowed for inout ports."); + break; + case NetNet::PINPUT: + pform_requires_sv(@4, "Default port value"); + ptmp->default_value = $4; + break; + case NetNet::POUTPUT: + pform_make_var_init(@3, name, $4); + break; + default: + break; + } + } /* Get the port declaration details, the port type and what not, from context data stored by the last port_declaration rule. */