diff --git a/ivtest/ivltests/sv_var_block.v b/ivtest/ivltests/sv_var_block.v new file mode 100644 index 000000000..e5a6590cb --- /dev/null +++ b/ivtest/ivltests/sv_var_block.v @@ -0,0 +1,50 @@ +// Check that the var keyword is supported for variable declarations in blocks + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +module test; + + bit failed = 1'b0; + + initial begin + var x; + var [7:0] y; + var signed [8:0] z; + var logic [9:0] w; + + x = 1'b1; + y = 8'd10; + z = -8'sd1; + w = 8'd20; + + `check(x, 1'b1) + `check(y, 10) + `check(z, -1) + `check(w, 20) + + // var should default to logic and allow x state + x = 1'bx; + y = 8'hxx; + z = 8'hxx; + w = 8'hxx; + + `check(x, 1'bx) + `check(y, 8'hxx) + `check(z, 8'hxx) + `check(w, 8'hxx) + + `check($bits(x), 1) + `check($bits(y), 8) + `check($bits(z), 9) + `check($bits(w), 10) + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_for.v b/ivtest/ivltests/sv_var_for.v new file mode 100644 index 000000000..f676125b0 --- /dev/null +++ b/ivtest/ivltests/sv_var_for.v @@ -0,0 +1,17 @@ +// Check that var keyword is supported in for loop variable declarations + +module test; + + initial begin + int j; + for (var int i = 0; i < 10; i++) begin + j = i; + end + if (j == 9) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_for_fail.v b/ivtest/ivltests/sv_var_for_fail.v new file mode 100644 index 000000000..827613d5c --- /dev/null +++ b/ivtest/ivltests/sv_var_for_fail.v @@ -0,0 +1,13 @@ +// Check that it is an error to not declare the data type in for loops, even +// when using var + +module test; + + initial begin + // The data type is not optional in a for loop, even when using var + for (var [7:0] i = 0; i < 10; i++) begin + end + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/sv_var_function.v b/ivtest/ivltests/sv_var_function.v new file mode 100644 index 000000000..829454ca7 --- /dev/null +++ b/ivtest/ivltests/sv_var_function.v @@ -0,0 +1,41 @@ +// Check that the var keyword is supported for function ports + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + return 1'b1; \ + end \ + return 1'b0; + +module test; + + function bit f1 (var int x); + `check(x, 10) + endfunction + + function bit f2 (input var int x); + `check(x, 20) + endfunction + + function bit f3 (var [7:0] x); + `check(x, 30) + endfunction + + function bit f4 (input var [7:0] x); + `check(x, 40) + endfunction + + initial begin + bit failed; + + failed = f1(10); + failed |= f2(20); + failed |= f3(30); + failed |= f4(40); + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_module.v b/ivtest/ivltests/sv_var_module.v new file mode 100644 index 000000000..0b63786dd --- /dev/null +++ b/ivtest/ivltests/sv_var_module.v @@ -0,0 +1,50 @@ +// Check that the var keyword is supported for variable declarations in modules + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +module test; + + var x; + var [7:0] y; + var signed [8:0] z; + var logic [9:0] w; + + bit failed = 1'b0; + + initial begin + x = 1'b1; + y = 8'd10; + z = -8'sd1; + w = 8'd20; + + `check(x, 1'b1) + `check(y, 10) + `check(z, -1) + `check(w, 20) + + // var should default to logic and allow x state + x = 1'bx; + y = 8'hxx; + z = 8'hxx; + w = 8'hxx; + + `check(x, 1'bx) + `check(y, 8'hxx) + `check(z, 8'hxx) + `check(w, 8'hxx) + + `check($bits(x), 1) + `check($bits(y), 8) + `check($bits(z), 9) + `check($bits(w), 10) + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_module_inout1.v b/ivtest/ivltests/sv_var_module_inout1.v new file mode 100644 index 000000000..4e07e8178 --- /dev/null +++ b/ivtest/ivltests/sv_var_module_inout1.v @@ -0,0 +1,11 @@ +// Check that using the var keyword for module ANSI inout ports results in an error + +module test #( + inout var x +); + + initial begin + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/sv_var_module_inout2.v b/ivtest/ivltests/sv_var_module_inout2.v new file mode 100644 index 000000000..cb0f68026 --- /dev/null +++ b/ivtest/ivltests/sv_var_module_inout2.v @@ -0,0 +1,10 @@ +// Check that using the var keyword for module non-ANSI inout ports results in an error + +module test; + inout var x; + + initial begin + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/sv_var_module_input1.v b/ivtest/ivltests/sv_var_module_input1.v new file mode 100644 index 000000000..d23a9dca0 --- /dev/null +++ b/ivtest/ivltests/sv_var_module_input1.v @@ -0,0 +1,61 @@ +// Check that the var keyword is supported for module ANSI input ports + +bit failed = 1'b0; + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +module M #( + parameter VAL_X = 0, + parameter VAL_Y = 0, + parameter VAL_Z = 0, + parameter VAL_W = 0 +) ( + input var x, + input var [7:0] y, + input var signed [7:0] z, + input var logic [7:0] w +); + + initial begin + `check(x, VAL_X) + `check(y, VAL_Y) + `check(z, VAL_Z) + `check(w, VAL_W) + end + +endmodule + +module test; + + M #( + .VAL_X (1'b1), + .VAL_Y (8'd10), + .VAL_Z (-8'sd1), + .VAL_W (8'd20) + ) i_m1 ( + .x (1'b1), + .y (8'd10), + .z (-8'sd1), + .w (8'd20) + ); + + // When unconnected it should default to x, rather z + M #( + .VAL_X (1'bx), + .VAL_Y (8'hx), + .VAL_Z (8'hx), + .VAL_W (8'hx) + ) i_m2 (); + + initial begin + #1 + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_module_input2.v b/ivtest/ivltests/sv_var_module_input2.v new file mode 100644 index 000000000..5ec7702fc --- /dev/null +++ b/ivtest/ivltests/sv_var_module_input2.v @@ -0,0 +1,60 @@ +// Check that the var keyword is supported for module non-ANSI input ports + +bit failed = 1'b0; + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +module M(x, y, z, w); + parameter VAL_X = 0; + parameter VAL_Y = 0; + parameter VAL_Z = 0; + parameter VAL_W = 0; + + input var x; + input var [7:0] y; + input var signed [7:0] z; + input var logic [7:0] w; + + initial begin + `check(x, VAL_X) + `check(y, VAL_Y) + `check(z, VAL_Z) + `check(w, VAL_W) + end + +endmodule + +module test; + + M #( + .VAL_X (1'b1), + .VAL_Y (8'd10), + .VAL_Z (-8'sd1), + .VAL_W (8'd20) + ) i_m1 ( + .x (1'b1), + .y (8'd10), + .z (-8'sd1), + .w (8'd20) + ); + + // When unconnected it should default to x, rather z + M #( + .VAL_X (1'bx), + .VAL_Y (8'hx), + .VAL_Z (8'hx), + .VAL_W (8'hx) + ) i_m2 (); + + initial begin + #1 + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_module_output1.v b/ivtest/ivltests/sv_var_module_output1.v new file mode 100644 index 000000000..1e64aff13 --- /dev/null +++ b/ivtest/ivltests/sv_var_module_output1.v @@ -0,0 +1,81 @@ +// Check that the var keyword is supported for module ANSI output ports + +bit failed = 1'b0; + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +module M #( + parameter VAL_X = 0, + parameter VAL_Y = 0, + parameter VAL_Z = 0, + parameter VAL_W = 0 +) ( + output var x, + output var [7:0] y, + output var signed [7:0] z, + output var logic [7:0] w +); + + assign x = VAL_X; + assign y = VAL_Y; + assign z = VAL_Z; + assign w = VAL_W; + +endmodule + +module test; + + logic x1; + logic x2; + logic [7:0] y1; + logic [7:0] y2; + logic signed [7:0] z1; + logic signed [7:0] z2; + logic [7:0] w1; + logic [7:0] w2; + + M #( + .VAL_X (1'b1), + .VAL_Y (10), + .VAL_Z (-1), + .VAL_W (20) + ) i_m1 ( + .x (x1), + .y (y1), + .z (z1), + .w (w1) + ); + + // The type for var should default to logic, check that the value can be X + M #( + .VAL_X (1'bx), + .VAL_Y (8'hxx), + .VAL_Z (8'hxx), + .VAL_W (8'hxx) + ) i_m2 ( + .x (x2), + .y (y2), + .z (z2), + .w (w2) + ); + + initial begin + `check(x1, 1'b1) + `check(y1, 10) + `check(z1, -1) + `check(w1, 20) + `check(x2, 1'bx) + `check(y2, 8'hxx) + `check(z2, 8'hxx) + `check(w2, 8'hxx) + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_module_output2.v b/ivtest/ivltests/sv_var_module_output2.v new file mode 100644 index 000000000..ca7962c9d --- /dev/null +++ b/ivtest/ivltests/sv_var_module_output2.v @@ -0,0 +1,80 @@ +// Check that the var keyword is supported for module non-ANSI output ports + +bit failed = 1'b0; + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +module M(x, y, z, w); + parameter VAL_X = 0; + parameter VAL_Y = 0; + parameter VAL_Z = 0; + parameter VAL_W = 0; + + output var x; + output var [7:0] y; + output var signed [7:0] z; + output var logic [7:0] w; + + assign x = VAL_X; + assign y = VAL_Y; + assign z = VAL_Z; + assign w = VAL_W; + +endmodule + +module test; + + logic x1; + logic x2; + logic [7:0] y1; + logic [7:0] y2; + logic signed [7:0] z1; + logic signed [7:0] z2; + logic [7:0] w1; + logic [7:0] w2; + + M #( + .VAL_X (1'b1), + .VAL_Y (10), + .VAL_Z (-1), + .VAL_W (20) + ) i_m1 ( + .x (x1), + .y (y1), + .z (z1), + .w (w1) + ); + + // The type for var should default to logic, check that the value can be X + M #( + .VAL_X (1'bx), + .VAL_Y (8'hxx), + .VAL_Z (8'hxx), + .VAL_W (8'hxx) + ) i_m2 ( + .x (x2), + .y (y2), + .z (z2), + .w (w2) + ); + + initial begin + `check(x1, 1'b1) + `check(y1, 10) + `check(z1, -1) + `check(w1, 20) + `check(x2, 1'bx) + `check(y2, 8'hxx) + `check(z2, 8'hxx) + `check(w2, 8'hxx) + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_package.v b/ivtest/ivltests/sv_var_package.v new file mode 100644 index 000000000..4030a9c7f --- /dev/null +++ b/ivtest/ivltests/sv_var_package.v @@ -0,0 +1,53 @@ +// Check that the var keyword is supported for variable declarations in packages + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +package P; + var x; + var [7:0] y; + var signed [8:0] z; + var logic [9:0] w; +endpackage + +module test; + import P::*; + + bit failed = 1'b0; + + initial begin + x = 1'b1; + y = 8'd10; + z = -8'sd1; + w = 8'd20; + + `check(x, 1'b1) + `check(y, 10) + `check(z, -1) + `check(w, 20) + + // var should default to logic and allow x state + x = 1'bx; + y = 8'hxx; + z = 8'hxx; + w = 8'hxx; + + `check(x, 1'bx) + `check(y, 8'hxx) + `check(z, 8'hxx) + `check(w, 8'hxx) + + `check($bits(x), 1) + `check($bits(y), 8) + `check($bits(z), 9) + `check($bits(w), 10) + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_var_task.v b/ivtest/ivltests/sv_var_task.v new file mode 100644 index 000000000..70ee3fb7f --- /dev/null +++ b/ivtest/ivltests/sv_var_task.v @@ -0,0 +1,48 @@ +// Check that the var keyword is supported for task ports + +bit failed = 1'b0; + +`define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \ + failed = 1'b1; \ + end + +module test; + + task t1 (var int x); + `check(x, 10) + endtask + + task t2 (input var int x, output var int y); + `check(x, 20) + y = x; + endtask + + task t3 (var [7:0] x); + `check(x, 30) + endtask + + task t4 (input var [7:0] x, output var [7:0] y); + `check(x, 40) + y = x; + endtask + + initial begin + int o1; + logic [7:0] o2; + + t1(10); + t2(20, o1); + t3(30); + t4(40, o2); + + `check(o1, 20) + `check(o2, 40) + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list index d21ffab1b..c01b065bb 100644 --- a/ivtest/regress-sv.list +++ b/ivtest/regress-sv.list @@ -694,8 +694,21 @@ sv_uwire1 normal,-g2009 ivltests sv_uwire2 normal,-g2009 ivltests sv_uwire3 normal,-g2009 ivltests sv_uwire4 normal,-g2009 ivltests +sv_var_block normal,-g2005-sv ivltests +sv_var_for normal,-g2005-sv ivltests +sv_var_for_fail CE,-g2005-sv ivltests +sv_var_function normal,-g2005-sv ivltests sv_var_init1 normal,-g2009 ivltests sv_var_init2 normal,-g2009 ivltests +sv_var_module normal,-g2005-sv ivltests +sv_var_module_inout1 CE,-g2005-sv ivltests +sv_var_module_inout2 CE,-g2005-sv ivltests +sv_var_module_input1 normal,-g2005-sv ivltests +sv_var_module_input2 normal,-g2005-sv ivltests +sv_var_module_output1 normal,-g2005-sv ivltests +sv_var_module_output2 normal,-g2005-sv ivltests +sv_var_package normal,-g2005-sv ivltests +sv_var_task normal,-g2005-sv ivltests sv_wildcard_import1 normal,-g2009 ivltests sv_wildcard_import2 normal,-g2009 ivltests sv_wildcard_import3 normal,-g2009 ivltests diff --git a/ivtest/regress-vlog95.list b/ivtest/regress-vlog95.list index 76d24a9ee..0f0b72526 100644 --- a/ivtest/regress-vlog95.list +++ b/ivtest/regress-vlog95.list @@ -942,6 +942,17 @@ sv_port_default10 normal,-g2009,-pallowsigned=1 ivltests sv_port_default11 normal,-g2009,-pallowsigned=1 ivltests sv_root_func normal,-g2009,-pallowsigned=1 ivltests gold=sv_root_func.gold sv_root_task normal,-g2009,-pallowsigned=1 ivltests gold=sv_root_task.gold +sv_var_block normal,-g2005-sv,-pallowsigned=1 ivltests +sv_var_for normal,-g2005-sv,-pallowsigned=1 ivltests +sv_var_function normal,-g2005-sv,-pallowsigned=1 ivltests +sv_var_module normal,-g2005-sv,-pallowsigned=1 ivltests +# Inputs can not be reg in Verilog 95, so the translated code will fail +sv_var_module_input1 TE,-g2005-sv,-pallowsigned=1 ivltests +sv_var_module_input2 TE,-g2005-sv,-pallowsigned=1 ivltests +sv_var_module_output1 normal,-g2005-sv,-pallowsigned=1 ivltests +sv_var_module_output2 normal,-g2005-sv,-pallowsigned=1 ivltests +sv_var_package normal,-g2005-sv,-pallowsigned=1 ivltests +sv_var_task normal,-g2005-sv,-pallowsigned=1 ivltests test_dispwided normal,-pallowsigned=1 ivltests gold=test_dispwided.gold test_inc_dec normal,-g2009,-pallowsigned=1 ivltests test_enumsystem normal,-g2009,-pallowsigned=1,ivltests/enumsystem.vhd ivltests