From 9ce28067100c43d6906083018a081768d85a33ed Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Wed, 23 Oct 2002 01:45:24 +0000
Subject: [PATCH]  Fix synth2 handling of aset/aclr signals where  flip-flops
 are split by begin-end blocks.

---
 design_dump.cc  |  9 +++++--
 ivl.def         |  1 +
 ivl_target.h    |  7 +++++-
 netlist.cc      | 16 ++++++++++++-
 netlist.h       | 12 +++++++++-
 synth2.cc       | 62 +++++++++++++++++++++++++++++++++++++++----------
 t-dll-api.cc    | 18 +++++++++++++-
 t-dll-expr.cc   | 38 +++++++++++++++++++++++++++++-
 t-dll.cc        | 13 +++++++++--
 t-dll.h         |  9 ++++++-
 tgt-stub/stub.c | 11 +++++++--
 11 files changed, 172 insertions(+), 24 deletions(-)

diff --git a/design_dump.cc b/design_dump.cc
index c305f7d90..379af6591 100644
--- a/design_dump.cc
+++ b/design_dump.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: design_dump.cc,v 1.134 2002/10/19 22:59:49 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.135 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 # include "config.h"
@@ -271,7 +271,8 @@ void NetConst::dump_node(ostream&o, unsigned ind) const
 void NetFF::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "LPM_FF: " << name()
-	<< " scope=" << (scope()? scope()->name() : "") << endl;
+	<< " scope=" << (scope()? scope()->name() : "")
+	<< " aset_value=" << aset_value_ << endl;
 
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
@@ -1003,6 +1004,10 @@ void Design::dump(ostream&o) const
 
 /*
  * $Log: design_dump.cc,v $
+ * Revision 1.135  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.134  2002/10/19 22:59:49  steve
  *  Redo the parameter vector support to allow
  *  parameter names in range expressions.
diff --git a/ivl.def b/ivl.def
index 2466d09f9..021fc6558 100644
--- a/ivl.def
+++ b/ivl.def
@@ -54,6 +54,7 @@ ivl_logic_pin
 ivl_logic_pins
 ivl_logic_udp
 
+ivl_lpm_aset_value
 ivl_lpm_async_clr
 ivl_lpm_async_set
 ivl_lpm_basename
diff --git a/ivl_target.h b/ivl_target.h
index 915e10f9c..41139af6c 100644
--- a/ivl_target.h
+++ b/ivl_target.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: ivl_target.h,v 1.107 2002/09/26 03:18:04 steve Exp $"
+#ident "$Id: ivl_target.h,v 1.108 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 #ifdef __cplusplus
@@ -615,6 +615,7 @@ extern unsigned       ivl_lpm_width(ivl_lpm_t net);
   /* IVL_LPM_FF */
 extern ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net);
 extern ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net);
+extern ivl_expr_t  ivl_lpm_aset_value(ivl_lpm_t net);
   /* IVL_LPM_FF IVL_LPM_RAM */
 extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
   /* IVL_LPM_UFUNC */
@@ -1090,6 +1091,10 @@ _END_DECL
 
 /*
  * $Log: ivl_target.h,v $
+ * Revision 1.108  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.107  2002/09/26 03:18:04  steve
  *  Generate vvp code for asynch set/reset of NetFF.
  *
diff --git a/netlist.cc b/netlist.cc
index 1e1c1382e..6e3539b78 100644
--- a/netlist.cc
+++ b/netlist.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: netlist.cc,v 1.200 2002/09/26 03:18:04 steve Exp $"
+#ident "$Id: netlist.cc,v 1.201 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 # include "config.h"
@@ -650,6 +650,16 @@ const Link& NetFF::pin_Q(unsigned w) const
       return pin(pn);
 }
 
+void NetFF::aset_value(const verinum&val)
+{
+      aset_value_ = val;
+}
+
+const verinum& NetFF::aset_value() const
+{
+      return aset_value_;
+}
+
 
 /*
  * The NetAddSub class represents an LPM_ADD_SUB device. The pinout is
@@ -2310,6 +2320,10 @@ const NetProc*NetTaskDef::proc() const
 
 /*
  * $Log: netlist.cc,v $
+ * Revision 1.201  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.200  2002/09/26 03:18:04  steve
  *  Generate vvp code for asynch set/reset of NetFF.
  *
diff --git a/netlist.h b/netlist.h
index 43321fac1..04cc25212 100644
--- a/netlist.h
+++ b/netlist.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: netlist.h,v 1.266 2002/10/21 01:42:08 steve Exp $"
+#ident "$Id: netlist.h,v 1.267 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 /*
@@ -671,9 +671,15 @@ class NetFF  : public NetNode {
       const Link& pin_Data(unsigned) const;
       const Link& pin_Q(unsigned) const;
 
+      void aset_value(const verinum&val);
+      const verinum& aset_value() const;
+
       virtual void dump_node(ostream&, unsigned ind) const;
       virtual bool emit_node(struct target_t*) const;
       virtual void functor_node(Design*des, functor_t*fun);
+
+    private:
+      verinum aset_value_;
 };
 
 
@@ -3077,6 +3083,10 @@ extern ostream& operator << (ostream&, NetNet::Type);
 
 /*
  * $Log: netlist.h,v $
+ * Revision 1.267  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.266  2002/10/21 01:42:08  steve
  *  Synthesizer support for synchronous begin-end blocks.
  *
diff --git a/synth2.cc b/synth2.cc
index d701cebc2..28126293e 100644
--- a/synth2.cc
+++ b/synth2.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: synth2.cc,v 1.16 2002/10/21 01:42:09 steve Exp $"
+#ident "$Id: synth2.cc,v 1.17 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 # include "config.h"
@@ -333,16 +333,24 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
 	    NetNet*tmp_out = new NetNet(scope, "tmp2", NetNet::WIRE,
 					tmp_set.count());
 
+	    verinum tmp_aset = ff->aset_value();
+
 	      /* Create a new DFF to handle this part of the begin-end
 		 block. Connect this NetFF to the associated pins of
-		 the existing wide NetFF device. */
+		 the existing wide NetFF device. While I'm at it, also
+		 copy the aset_value bits for the new ff device. */
 	    NetFF*ff2 = new NetFF(scope, scope->local_hsymbol().c_str(),
 				  tmp_out->pin_count());
 	    des->add_node(ff2);
 
+	    verinum aset_value2 (verinum::V1, ff2->width());
 	    for (unsigned idx = 0 ;  idx < ff2->width() ;  idx += 1) {
-		  connect(ff->pin_Data(idx+offset), ff2->pin_Data(idx));
-		  connect(ff->pin_Q(idx+offset), ff2->pin_Q(idx));
+		  unsigned ptr = find_nexus_in_set(nex_map, tmp_set[idx]);
+		  connect(ff->pin_Data(ptr), ff2->pin_Data(idx));
+		  connect(ff->pin_Q(ptr), ff2->pin_Q(idx));
+
+		  if (ptr < tmp_aset.len())
+			aset_value2.set(idx, tmp_aset[ptr]);
 	    }
 	    if (ff->pin_Aclr().is_linked())
 		  connect(ff->pin_Aclr(),  ff2->pin_Aclr());
@@ -353,6 +361,23 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
 	    if (ff->pin_Enable().is_linked())
 		  connect(ff->pin_Enable(),ff2->pin_Enable());
 
+	      /* Remember to store the aset value into the new FF. If
+		 this leads to an Aset value of 0 (and Aclr is not
+		 otherwise used) then move the Aset input to Aclr. */
+	    if (tmp_aset.len() == ff->width()) {
+
+		  if ((aset_value2.as_ulong() == 0)
+		      && ff2->pin_Aset().is_linked()
+		      && !ff2->pin_Aclr().is_linked()) {
+
+			connect(ff2->pin_Aclr(), ff2->pin_Aset());
+			ff2->pin_Aset().unlink();
+
+		  } else {
+			ff2->aset_value(aset_value2);
+		  }
+	    }
+
 	      /* Now go on with the synchronous synthesis for this
 		 subset of the statement. */
 	    bool ok_flag = cur->synth_sync(des, scope, ff2, tmp_map,
@@ -415,16 +440,25 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope, NetFF*ff,
 		  if_->synth_async(des, scope, nex_map, asig);
 
 		  assert(asig->pin_count() == ff->width());
-		  assert(asig->pin(0).nexus()->drivers_constant());
-		  switch (asig->pin(0).nexus()->driven_value()) {
-		      case verinum::V0:
+
+		    /* Collect the set/reset value into a verinum. If
+		       this turns out to be entirely 0 values, then
+		       use the Aclr input. Otherwise, use the Aset
+		       input and save the set value. */
+		  verinum tmp (verinum::V0, ff->width());
+		  for (unsigned bit = 0 ;  bit < ff->width() ;  bit += 1) {
+
+			assert(asig->pin(bit).nexus()->drivers_constant());
+			tmp.set(bit, asig->pin(bit).nexus()->driven_value());
+		  }
+
+		  assert(tmp.is_defined());
+		  if (tmp.as_ulong() == 0) {
 			connect(ff->pin_Aclr(), ce->pin(0));
-			break;
-		      case verinum::V1:
+
+		  } else {
 			connect(ff->pin_Aset(), ce->pin(0));
-			break;
-		      default:
-			assert(0);
+			ff->aset_value(tmp);
 		  }
 
 		  delete asig;
@@ -655,6 +689,10 @@ void synth2(Design*des)
 
 /*
  * $Log: synth2.cc,v $
+ * Revision 1.17  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.16  2002/10/21 01:42:09  steve
  *  Synthesizer support for synchronous begin-end blocks.
  *
diff --git a/t-dll-api.cc b/t-dll-api.cc
index 7a5f053df..f912255b3 100644
--- a/t-dll-api.cc
+++ b/t-dll-api.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: t-dll-api.cc,v 1.87 2002/09/26 03:18:04 steve Exp $"
+#ident "$Id: t-dll-api.cc,v 1.88 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 # include "config.h"
@@ -577,6 +577,18 @@ extern "C" ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net)
       }
 }
 
+extern "C" ivl_expr_t ivl_lpm_aset_value(ivl_lpm_t net)
+{
+      assert(net);
+      switch (net->type) {
+	  case IVL_LPM_FF:
+	  case IVL_LPM_RAM:
+	    return net->u_.ff.aset_value;
+	  default:
+	    assert(0);
+	    return 0;
+      }
+}
 extern "C" ivl_scope_t ivl_lpm_define(ivl_lpm_t net)
 {
       assert(net);
@@ -1573,6 +1585,10 @@ extern "C" ivl_statement_t ivl_stmt_sub_stmt(ivl_statement_t net)
 
 /*
  * $Log: t-dll-api.cc,v $
+ * Revision 1.88  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.87  2002/09/26 03:18:04  steve
  *  Generate vvp code for asynch set/reset of NetFF.
  *
diff --git a/t-dll-expr.cc b/t-dll-expr.cc
index d6054fa4f..bcc95a176 100644
--- a/t-dll-expr.cc
+++ b/t-dll-expr.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: t-dll-expr.cc,v 1.28 2002/08/12 01:35:00 steve Exp $"
+#ident "$Id: t-dll-expr.cc,v 1.29 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 # include "config.h"
@@ -103,6 +103,38 @@ void dll_target::mul_expr_by_const_(long val)
       expr_ = tmps;
 }
 
+ivl_expr_t dll_target::expr_from_value_(const verinum&val)
+{
+      ivl_expr_t expr = (ivl_expr_t)calloc(1, sizeof(struct ivl_expr_s));
+      assert(expr);
+
+      unsigned idx;
+      char*bits;
+      expr->type_ = IVL_EX_NUMBER;
+      expr->width_= val.len();
+      expr->signed_ = val.has_sign()? 1 : 0;
+      expr->u_.number_.bits_ = bits = (char*)malloc(expr->width_);
+      for (idx = 0 ;  idx < expr->width_ ;  idx += 1)
+	    switch (val.get(idx)) {
+		case verinum::V0:
+		  bits[idx] = '0';
+		  break;
+		case verinum::V1:
+		  bits[idx] = '1';
+		  break;
+		case verinum::Vx:
+		  bits[idx] = 'x';
+		  break;
+		case verinum::Vz:
+		  bits[idx] = 'z';
+		  break;
+		default:
+		  assert(0);
+	    }
+
+      return expr;
+}
+
 void dll_target::expr_binary(const NetEBinary*net)
 {
       assert(expr_ == 0);
@@ -458,6 +490,10 @@ void dll_target::expr_unary(const NetEUnary*net)
 
 /*
  * $Log: t-dll-expr.cc,v $
+ * Revision 1.29  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.28  2002/08/12 01:35:00  steve
  *  conditional ident string using autoconfig.
  *
diff --git a/t-dll.cc b/t-dll.cc
index 5cf513de6..748703c6a 100644
--- a/t-dll.cc
+++ b/t-dll.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: t-dll.cc,v 1.96 2002/09/26 03:18:04 steve Exp $"
+#ident "$Id: t-dll.cc,v 1.97 2002/10/23 01:47:18 steve Exp $"
 #endif
 
 # include "config.h"
@@ -1376,9 +1376,14 @@ void dll_target::lpm_ff(const NetFF*net)
 	    assert(nex->t_cookie());
 	    obj->u_.ff.aset = (ivl_nexus_t) nex->t_cookie();
 	    assert(obj->u_.ff.aset);
-	    nexus_lpm_add(obj->u_.ff.aclr, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
+	    nexus_lpm_add(obj->u_.ff.aset, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
+
+	    verinum tmp = net->aset_value();
+	    obj->u_.ff.aset_value = expr_from_value_(tmp);
+
       } else {
 	    obj->u_.ff.aset = 0;
+	    obj->u_.ff.aset_value = 0;
       }
 
       if (obj->u_.ff.width == 1) {
@@ -1974,6 +1979,10 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
 
 /*
  * $Log: t-dll.cc,v $
+ * Revision 1.97  2002/10/23 01:47:18  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.96  2002/09/26 03:18:04  steve
  *  Generate vvp code for asynch set/reset of NetFF.
  *
diff --git a/t-dll.h b/t-dll.h
index 323d0fe17..ba8d3dce3 100644
--- a/t-dll.h
+++ b/t-dll.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: t-dll.h,v 1.94 2002/09/26 03:18:04 steve Exp $"
+#ident "$Id: t-dll.h,v 1.95 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 # include  "target.h"
@@ -154,6 +154,8 @@ struct dll_target  : public target_t, public expr_scan_t {
 
       void sub_off_from_expr_(long);
       void mul_expr_by_const_(long);
+
+      static ivl_expr_t expr_from_value_(const verinum&that);
 };
 
 /*
@@ -282,6 +284,7 @@ struct ivl_lpm_s {
 			ivl_nexus_t pin;
 		  } s;
 		  ivl_memory_t mem; // ram only
+		  ivl_expr_t aset_value;
 	    } ff;
 
 	    struct ivl_lpm_mux_s {
@@ -619,6 +622,10 @@ struct ivl_statement_s {
 
 /*
  * $Log: t-dll.h,v $
+ * Revision 1.95  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.94  2002/09/26 03:18:04  steve
  *  Generate vvp code for asynch set/reset of NetFF.
  *
diff --git a/tgt-stub/stub.c b/tgt-stub/stub.c
index fea9d2c7f..1d5abf212 100644
--- a/tgt-stub/stub.c
+++ b/tgt-stub/stub.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: stub.c,v 1.69 2002/09/26 03:18:04 steve Exp $"
+#ident "$Id: stub.c,v 1.70 2002/10/23 01:45:24 steve Exp $"
 #endif
 
 # include "config.h"
@@ -195,9 +195,12 @@ static void show_lpm(ivl_lpm_t net)
 		      fprintf(out, "    Aclr: %s\n",
 			      ivl_nexus_name(ivl_lpm_async_clr(net)));
 
-		if (ivl_lpm_async_set(net))
+		if (ivl_lpm_async_set(net)) {
 		      fprintf(out, "    Aset: %s\n",
 			      ivl_nexus_name(ivl_lpm_async_set(net)));
+		      if (ivl_lpm_aset_value(net))
+			    show_expression(ivl_lpm_aset_value(net), 10);
+		}
 
 		for (idx = 0 ;  idx < width ;  idx += 1)
 		      fprintf(out, "    Data %u: %s\n", idx,
@@ -725,6 +728,10 @@ int target_design(ivl_design_t des)
 
 /*
  * $Log: stub.c,v $
+ * Revision 1.70  2002/10/23 01:45:24  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
  * Revision 1.69  2002/09/26 03:18:04  steve
  *  Generate vvp code for asynch set/reset of NetFF.
  *