Resize vectors to mismatched ports
It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
This commit is contained in:
Stephen Williams
parent
8fe3cc5318
commit
9c99b002ba
138
PGate.h
138
PGate.h
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@ -27,12 +27,11 @@
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# include "named.h"
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# include "LineInfo.h"
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# include "PDelays.h"
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# include "netlist.h"
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# include <map>
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# include <string>
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class PExpr;
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class PUdp;
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class Design;
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class NetScope;
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class Module;
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/*
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@ -235,137 +234,10 @@ class PGModule : public PGate {
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void elaborate_udp_(Design*, PUdp *udp, NetScope*scope) const;
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void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
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bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
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NetNet*resize_net_to_port_(Design*des, NetScope*scope,
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NetNet*sig, unsigned port_wid,
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NetNet::PortType dir) const;
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};
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/*
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* $Log: PGate.h,v $
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* Revision 1.32 2006/04/10 00:37:42 steve
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* Add support for generate loops w/ wires and gates.
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*
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* Revision 1.31 2006/01/03 05:22:14 steve
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* Handle complex net node delays.
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*
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* Revision 1.30 2006/01/02 05:33:19 steve
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* Node delays can be more general expressions in structural contexts.
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*
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* Revision 1.29 2004/10/04 01:10:52 steve
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* Clean up spurious trailing white space.
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*
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* Revision 1.28 2004/03/08 00:47:44 steve
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* primitive ports can bind bi name.
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*
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* Revision 1.27 2004/02/20 18:53:33 steve
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* Addtrbute keys are perm_strings.
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*
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* Revision 1.26 2004/02/18 17:11:54 steve
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* Use perm_strings for named langiage items.
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*
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* Revision 1.25 2003/03/06 04:37:12 steve
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* lex_strings.add module names earlier.
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*
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* Revision 1.24 2002/08/12 01:34:58 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.23 2002/05/23 03:08:51 steve
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* Add language support for Verilog-2001 attribute
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* syntax. Hook this support into existing $attribute
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* handling, and add number and void value types.
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*
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* Add to the ivl_target API new functions for access
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* of complex attributes attached to gates.
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*
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* Revision 1.22 2001/11/22 06:20:59 steve
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* Use NetScope instead of string for scope path.
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*
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* Revision 1.21 2001/10/21 00:42:47 steve
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* Module types in pform are char* instead of string.
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*
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* Revision 1.20 2001/10/19 01:55:32 steve
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* Method to get the type_ member
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*
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* Revision 1.19 2001/04/22 23:09:45 steve
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* More UDP consolidation from Stephan Boettcher.
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*
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* Revision 1.18 2000/05/06 15:41:56 steve
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* Carry assignment strength to pform.
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*
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* Revision 1.17 2000/05/02 16:27:38 steve
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* Move signal elaboration to a seperate pass.
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*
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* Revision 1.16 2000/03/29 04:37:10 steve
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* New and improved combinational primitives.
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*
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* Revision 1.15 2000/03/08 04:36:53 steve
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* Redesign the implementation of scopes and parameters.
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* I now generate the scopes and notice the parameters
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* in a separate pass over the pform. Once the scopes
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* are generated, I can process overrides and evalutate
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* paremeters before elaboration begins.
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*
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* Revision 1.14 2000/02/23 02:56:53 steve
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* Macintosh compilers do not support ident.
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*
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* Revision 1.13 2000/02/18 05:15:02 steve
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* Catch module instantiation arrays.
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*
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* Revision 1.12 2000/01/09 05:50:48 steve
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* Support named parameter override lists.
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*
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* Revision 1.11 1999/12/11 05:45:41 steve
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* Fix support for attaching attributes to primitive gates.
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*
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* Revision 1.10 1999/09/04 19:11:46 steve
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* Add support for delayed non-blocking assignments.
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*
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* Revision 1.9 1999/08/23 16:48:39 steve
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* Parameter overrides support from Peter Monta
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* AND and XOR support wide expressions.
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*
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* Revision 1.8 1999/08/01 21:18:55 steve
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* elaborate rise/fall/decay for continuous assign.
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*
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* Revision 1.7 1999/08/01 16:34:50 steve
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* Parse and elaborate rise/fall/decay times
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* for gates, and handle the rules for partial
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* lists of times.
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*
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* Revision 1.6 1999/05/29 02:36:17 steve
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* module parameter bind by name.
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*
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* Revision 1.5 1999/05/10 00:16:58 steve
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* Parse and elaborate the concatenate operator
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* in structural contexts, Replace vector<PExpr*>
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* and list<PExpr*> with svector<PExpr*>, evaluate
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* constant expressions with parameters, handle
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* memories as lvalues.
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*
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* Parse task declarations, integer types.
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*
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* Revision 1.4 1999/02/15 02:06:15 steve
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* Elaborate gate ranges.
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*
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* Revision 1.3 1999/01/25 05:45:56 steve
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* Add the LineInfo class to carry the source file
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* location of things. PGate, Statement and PProcess.
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*
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* elaborate handles module parameter mismatches,
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* missing or incorrect lvalues for procedural
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* assignment, and errors are propogated to the
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* top of the elaboration call tree.
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*
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* Attach line numbers to processes, gates and
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* assignment statements.
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*
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* Revision 1.2 1998/12/01 00:42:13 steve
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* Elaborate UDP devices,
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* Support UDP type attributes, and
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* pass those attributes to nodes that
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* are instantiated by elaboration,
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* Put modules into a map instead of
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* a simple list.
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*
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* Revision 1.1 1998/11/03 23:28:54 steve
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* Introduce verilog to CVS.
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*
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*/
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#endif
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63
elaborate.cc
63
elaborate.cc
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@ -783,6 +783,64 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
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}
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}
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NetNet*PGModule::resize_net_to_port_(Design*des, NetScope*scope,
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NetNet*sig, unsigned port_wid,
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NetNet::PortType dir) const
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{
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ivl_assert(*this, dir != NetNet::NOT_A_PORT);
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ivl_assert(*this, dir != NetNet::PIMPLICIT);
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NetNet*tmp = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, port_wid);
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tmp->local_flag(true);
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tmp->set_line(*sig);
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NetPartSelect*node = 0;
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switch (dir) {
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case NetNet::POUTPUT:
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if (tmp->vector_width() > sig->vector_width()) {
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node = new NetPartSelect(tmp, 0, sig->vector_width(),
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NetPartSelect::VP);
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} else {
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node = new NetPartSelect(tmp, 0, sig->vector_width(),
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NetPartSelect::PV);
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}
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connect(node->pin(0), sig->pin(0));
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break;
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case NetNet::PINPUT:
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if (tmp->vector_width() > sig->vector_width()) {
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node = new NetPartSelect(sig, 0, tmp->vector_width(),
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NetPartSelect::PV);
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} else {
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node = new NetPartSelect(sig, 0, tmp->vector_width(),
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NetPartSelect::VP);
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}
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connect(node->pin(0), tmp->pin(0));
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break;
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case NetNet::PINOUT:
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if (sig->vector_width() > tmp->vector_width()) {
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node = new NetPartSelect(sig, 0, tmp->vector_width(),
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NetPartSelect::BI);
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connect(node->pin(0), tmp->pin(0));
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} else {
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node = new NetPartSelect(tmp, 0, sig->vector_width(),
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NetPartSelect::BI);
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connect(node->pin(0), sig->pin(0));
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}
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break;
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default:
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ivl_assert(*this, 0);
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}
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des->add_node(node);
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return tmp;
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}
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/*
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* Instantiate a module by recursively elaborating it. Set the path of
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* the recursive elaboration so that signal names get properly
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@ -1113,12 +1171,17 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
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<< (prts_vector_width-sig->vector_width())
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<< " high bits of the port unconnected."
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<< endl;
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} else {
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cerr << get_line() << ": : Leaving "
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<< (sig->vector_width()-prts_vector_width)
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<< " high bits of the expression dangling."
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<< endl;
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}
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sig = resize_net_to_port_(des, scope, sig, prts_vector_width,
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prts[0]->port_type());
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}
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// Connect the sig expression that is the context of the
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