diff --git a/PGate.h b/PGate.h
index 34f09dbb5..9f4f14469 100644
--- a/PGate.h
+++ b/PGate.h
@@ -27,12 +27,11 @@
 # include  "named.h"
 # include  "LineInfo.h"
 # include  "PDelays.h"
+# include  "netlist.h"
 # include  <map>
 # include  <string>
 class PExpr;
 class PUdp;
-class Design;
-class NetScope;
 class Module;
 
 /*
@@ -235,137 +234,10 @@ class PGModule  : public PGate {
       void elaborate_udp_(Design*, PUdp  *udp, NetScope*scope) const;
       void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
       bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
+
+      NetNet*resize_net_to_port_(Design*des, NetScope*scope,
+				 NetNet*sig, unsigned port_wid,
+				 NetNet::PortType dir) const;
 };
 
-/*
- * $Log: PGate.h,v $
- * Revision 1.32  2006/04/10 00:37:42  steve
- *  Add support for generate loops w/ wires and gates.
- *
- * Revision 1.31  2006/01/03 05:22:14  steve
- *  Handle complex net node delays.
- *
- * Revision 1.30  2006/01/02 05:33:19  steve
- *  Node delays can be more general expressions in structural contexts.
- *
- * Revision 1.29  2004/10/04 01:10:52  steve
- *  Clean up spurious trailing white space.
- *
- * Revision 1.28  2004/03/08 00:47:44  steve
- *  primitive ports can bind bi name.
- *
- * Revision 1.27  2004/02/20 18:53:33  steve
- *  Addtrbute keys are perm_strings.
- *
- * Revision 1.26  2004/02/18 17:11:54  steve
- *  Use perm_strings for named langiage items.
- *
- * Revision 1.25  2003/03/06 04:37:12  steve
- *  lex_strings.add module names earlier.
- *
- * Revision 1.24  2002/08/12 01:34:58  steve
- *  conditional ident string using autoconfig.
- *
- * Revision 1.23  2002/05/23 03:08:51  steve
- *  Add language support for Verilog-2001 attribute
- *  syntax. Hook this support into existing $attribute
- *  handling, and add number and void value types.
- *
- *  Add to the ivl_target API new functions for access
- *  of complex attributes attached to gates.
- *
- * Revision 1.22  2001/11/22 06:20:59  steve
- *  Use NetScope instead of string for scope path.
- *
- * Revision 1.21  2001/10/21 00:42:47  steve
- *  Module types in pform are char* instead of string.
- *
- * Revision 1.20  2001/10/19 01:55:32  steve
- *  Method to get the type_ member
- *
- * Revision 1.19  2001/04/22 23:09:45  steve
- *  More UDP consolidation from Stephan Boettcher.
- *
- * Revision 1.18  2000/05/06 15:41:56  steve
- *  Carry assignment strength to pform.
- *
- * Revision 1.17  2000/05/02 16:27:38  steve
- *  Move signal elaboration to a seperate pass.
- *
- * Revision 1.16  2000/03/29 04:37:10  steve
- *  New and improved combinational primitives.
- *
- * Revision 1.15  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
- *
- * Revision 1.14  2000/02/23 02:56:53  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.13  2000/02/18 05:15:02  steve
- *  Catch module instantiation arrays.
- *
- * Revision 1.12  2000/01/09 05:50:48  steve
- *  Support named parameter override lists.
- *
- * Revision 1.11  1999/12/11 05:45:41  steve
- *  Fix support for attaching attributes to primitive gates.
- *
- * Revision 1.10  1999/09/04 19:11:46  steve
- *  Add support for delayed non-blocking assignments.
- *
- * Revision 1.9  1999/08/23 16:48:39  steve
- *  Parameter overrides support from Peter Monta
- *  AND and XOR support wide expressions.
- *
- * Revision 1.8  1999/08/01 21:18:55  steve
- *  elaborate rise/fall/decay for continuous assign.
- *
- * Revision 1.7  1999/08/01 16:34:50  steve
- *  Parse and elaborate rise/fall/decay times
- *  for gates, and handle the rules for partial
- *  lists of times.
- *
- * Revision 1.6  1999/05/29 02:36:17  steve
- *  module parameter bind by name.
- *
- * Revision 1.5  1999/05/10 00:16:58  steve
- *  Parse and elaborate the concatenate operator
- *  in structural contexts, Replace vector<PExpr*>
- *  and list<PExpr*> with svector<PExpr*>, evaluate
- *  constant expressions with parameters, handle
- *  memories as lvalues.
- *
- *  Parse task declarations, integer types.
- *
- * Revision 1.4  1999/02/15 02:06:15  steve
- *  Elaborate gate ranges.
- *
- * Revision 1.3  1999/01/25 05:45:56  steve
- *  Add the LineInfo class to carry the source file
- *  location of things. PGate, Statement and PProcess.
- *
- *  elaborate handles module parameter mismatches,
- *  missing or incorrect lvalues for procedural
- *  assignment, and errors are propogated to the
- *  top of the elaboration call tree.
- *
- *  Attach line numbers to processes, gates and
- *  assignment statements.
- *
- * Revision 1.2  1998/12/01 00:42:13  steve
- *  Elaborate UDP devices,
- *  Support UDP type attributes, and
- *  pass those attributes to nodes that
- *  are instantiated by elaboration,
- *  Put modules into a map instead of
- *  a simple list.
- *
- * Revision 1.1  1998/11/03 23:28:54  steve
- *  Introduce verilog to CVS.
- *
- */
 #endif
diff --git a/elaborate.cc b/elaborate.cc
index 7e3d5d4a5..1e78e1342 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -783,6 +783,64 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
       }
 }
 
+NetNet*PGModule::resize_net_to_port_(Design*des, NetScope*scope,
+				     NetNet*sig, unsigned port_wid,
+				     NetNet::PortType dir) const
+{
+      ivl_assert(*this, dir != NetNet::NOT_A_PORT);
+      ivl_assert(*this, dir != NetNet::PIMPLICIT);
+
+      NetNet*tmp = new NetNet(scope, scope->local_symbol(),
+			      NetNet::WIRE, port_wid);
+      tmp->local_flag(true);
+      tmp->set_line(*sig);
+
+      NetPartSelect*node = 0;
+
+      switch (dir) {
+	  case NetNet::POUTPUT:
+	    if (tmp->vector_width() > sig->vector_width()) {
+		  node = new NetPartSelect(tmp, 0, sig->vector_width(),
+					   NetPartSelect::VP);
+	    } else {
+		  node = new NetPartSelect(tmp, 0, sig->vector_width(),
+					  NetPartSelect::PV);
+	    }
+	    connect(node->pin(0), sig->pin(0));
+	    break;
+
+	  case NetNet::PINPUT:
+	    if (tmp->vector_width() > sig->vector_width()) {
+		  node = new NetPartSelect(sig, 0, tmp->vector_width(),
+					   NetPartSelect::PV);
+	    } else {
+		  node = new NetPartSelect(sig, 0, tmp->vector_width(),
+					   NetPartSelect::VP);
+	    }
+	    connect(node->pin(0), tmp->pin(0));
+	    break;
+
+	  case NetNet::PINOUT:
+	    if (sig->vector_width() > tmp->vector_width()) {
+		  node = new NetPartSelect(sig, 0, tmp->vector_width(),
+					   NetPartSelect::BI);
+		  connect(node->pin(0), tmp->pin(0));
+	    } else {
+		  node = new NetPartSelect(tmp, 0, sig->vector_width(),
+					   NetPartSelect::BI);
+		  connect(node->pin(0), sig->pin(0));
+	    }
+	    break;
+
+	  default:
+	    ivl_assert(*this, 0);
+      }
+
+      des->add_node(node);
+
+      return tmp;
+}
+
 /*
  * Instantiate a module by recursively elaborating it. Set the path of
  * the recursive elaboration so that signal names get properly
@@ -1113,12 +1171,17 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 			     << (prts_vector_width-sig->vector_width())
 			     << " high bits of the port unconnected."
 			     << endl;
+
+
 		  } else {
 			cerr << get_line() << ":        : Leaving "
 			     << (sig->vector_width()-prts_vector_width)
 			     << " high bits of the expression dangling."
 			     << endl;
 		  }
+
+		  sig = resize_net_to_port_(des, scope, sig, prts_vector_width,
+					    prts[0]->port_type());
 	    }
 
 	      // Connect the sig expression that is the context of the