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Allow `parameter` in generate blocks for SystemVerilog 

SystemVerilog allows to use the `parameter` keyword in a generate
block. If used in a generate block it behaves like a `localparam` and
cannot be overridden.

This is described in section 27.2 ("Generate constructs - Overview") of the
LRM (1800-2017).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-01-25 11:24:57 +01:00
parent 9f5ad34e35
commit 9a94e6b43b
1 changed files with 7 additions and 2 deletions
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7
pform.cc
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@ -3236,9 +3236,14 @@ void pform_set_parameter(const struct vlltype&loc,
bool overridable = !is_local; bool overridable = !is_local;
if (scope == pform_cur_generate && !is_local) { if (scope == pform_cur_generate && !is_local) {
VLerror("parameter declarations are not permitted in generate blocks"); if (!gn_system_verilog()) {
VLerror(loc, "parameter declarations are not permitted in generate blocks");
return; return;
} }
// SystemVerilog allows `parameter` in generate blocks, but it has
// the same semantics as `localparam` in that scope.
overridable = false;
}
assert(expr); assert(expr);
Module::param_expr_t*parm = new Module::param_expr_t(); Module::param_expr_t*parm = new Module::param_expr_t();