From 9a94e6b43b0a3aa0ee57c6fe8e2d41c2e7a8711f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 25 Jan 2022 11:24:57 +0100 Subject: [PATCH] Allow `parameter` in generate blocks for SystemVerilog SystemVerilog allows to use the `parameter` keyword in a generate block. If used in a generate block it behaves like a `localparam` and cannot be overridden. This is described in section 27.2 ("Generate constructs - Overview") of the LRM (1800-2017). Signed-off-by: Lars-Peter Clausen --- pform.cc | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/pform.cc b/pform.cc index 3498417c8..4de09e481 100644 --- a/pform.cc +++ b/pform.cc @@ -3236,8 +3236,13 @@ void pform_set_parameter(const struct vlltype&loc, bool overridable = !is_local; if (scope == pform_cur_generate && !is_local) { - VLerror("parameter declarations are not permitted in generate blocks"); - return; + if (!gn_system_verilog()) { + VLerror(loc, "parameter declarations are not permitted in generate blocks"); + return; + } + // SystemVerilog allows `parameter` in generate blocks, but it has + // the same semantics as `localparam` in that scope. + overridable = false; } assert(expr);