Generate signals and sensitivity list for @(..) statement

tgt-vhdl/stmt.cc

@@ -180,6 +180,16 @@ static int draw_wait(vhdl_process *proc, ivl_statement_t stmt)
                const char *signame = ivl_signal_basename(sig);
                std::cout << "signal " << signame << std::endl;
 
+               if (!proc->get_parent()->have_declared(signame)) {
+                  // First time this signal has been encountered
+                  vhdl_scalar_type *std_logic =
+                     new vhdl_scalar_type("std_logic");
+                  vhdl_signal_decl *sig_decl =
+                     new vhdl_signal_decl(signame, std_logic);
+                  
+                  proc->get_parent()->add_decl(sig_decl);
+               }
+                  
                proc->add_sensitivity(signame);
                return 0;
             }

tgt-vhdl/vhdl_element.cc

@@ -127,6 +127,11 @@ void vhdl_entity::requires_package(const char *spec)
 
 void vhdl_entity::emit(std::ofstream &of, int level) const
 {
+   // Pretty much every design will use std_logic so we
+   // might as well include it by default
+   of << "library ieee;" << std::endl;
+   of << "use ieee.std_logic_1164.all;" << std::endl;
+   
    for (std::list<std::string>::const_iterator it = uses_.begin();
         it != uses_.end();
         ++it)
@@ -201,6 +206,20 @@ bool vhdl_arch::have_declared_component(const std::string &name) const
    return false;
 }
 
+/*
+ * True if any declaration of `name' has been added to the
+ * architecture.
+ */
+bool vhdl_arch::have_declared(const std::string &name) const
+{
+   decl_list_t::const_iterator it;
+   for (it = decls_.begin(); it != decls_.end(); ++it) {
+      if ((*it)->get_name() == name)
+         return true;
+   }
+   return false;
+}
+
 vhdl_arch *vhdl_conc_stmt::get_parent() const
 {
    assert(parent_);
@@ -337,6 +356,19 @@ void vhdl_var_decl::emit(std::ofstream &of, int level) const
    emit_comment(of, level, true);
 }
 
+vhdl_signal_decl::~vhdl_signal_decl()
+{
+   delete type_;
+}
+
+void vhdl_signal_decl::emit(std::ofstream &of, int level) const
+{
+   of << "signal " << name_ << " : ";
+   type_->emit(of, level);
+   of << ";";
+   emit_comment(of, level, true);
+}
+
 void vhdl_expr_list::add_expr(vhdl_expr *e)
 {
    exprs_.push_back(e);

tgt-vhdl/vhdl_element.hh

@@ -220,6 +220,21 @@ private:
 };
 
 
+/*
+ * A signal declaration in architecture.
+ */
+class vhdl_signal_decl : public vhdl_decl {
+public:
+   vhdl_signal_decl(const char *name, vhdl_type *type)
+      : vhdl_decl(name), type_(type) {}
+   ~vhdl_signal_decl();
+
+   void emit(std::ofstream &of, int level) const;
+private:
+   vhdl_type *type_;
+};
+
+
 /*
  * Instantiation of component. This is really only a placeholder
  * at the moment until the port mappings are worked out.
@@ -269,6 +284,7 @@ public:
 
    void emit(std::ofstream &of, int level=0) const;
    bool have_declared_component(const std::string &name) const;
+   bool have_declared(const std::string &name) const;
    void add_decl(vhdl_decl *decl);
    void add_stmt(vhdl_conc_stmt *stmt);
    vhdl_entity *get_parent() const;