From 96cf1907203e511d0752fbf5dfda07b07aafa3e3 Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Fri, 6 Jun 2008 17:56:52 +0100 Subject: [PATCH] Generate signals and sensitivity list for @(..) statement --- tgt-vhdl/stmt.cc | 12 +++++++++++- tgt-vhdl/vhdl_element.cc | 34 +++++++++++++++++++++++++++++++++- tgt-vhdl/vhdl_element.hh | 18 +++++++++++++++++- 3 files changed, 61 insertions(+), 3 deletions(-) diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc index 30637d7e1..8d98a52d4 100644 --- a/tgt-vhdl/stmt.cc +++ b/tgt-vhdl/stmt.cc @@ -179,7 +179,17 @@ static int draw_wait(vhdl_process *proc, ivl_statement_t stmt) if ((sig = ivl_nexus_ptr_sig(nexus_ptr))) { const char *signame = ivl_signal_basename(sig); std::cout << "signal " << signame << std::endl; - + + if (!proc->get_parent()->have_declared(signame)) { + // First time this signal has been encountered + vhdl_scalar_type *std_logic = + new vhdl_scalar_type("std_logic"); + vhdl_signal_decl *sig_decl = + new vhdl_signal_decl(signame, std_logic); + + proc->get_parent()->add_decl(sig_decl); + } + proc->add_sensitivity(signame); return 0; } diff --git a/tgt-vhdl/vhdl_element.cc b/tgt-vhdl/vhdl_element.cc index bd59b40d2..073ddc267 100644 --- a/tgt-vhdl/vhdl_element.cc +++ b/tgt-vhdl/vhdl_element.cc @@ -106,7 +106,7 @@ vhdl_entity::vhdl_entity(const char *name, const char *derived_from, } vhdl_entity::~vhdl_entity() -{ +{ delete arch_; } @@ -127,6 +127,11 @@ void vhdl_entity::requires_package(const char *spec) void vhdl_entity::emit(std::ofstream &of, int level) const { + // Pretty much every design will use std_logic so we + // might as well include it by default + of << "library ieee;" << std::endl; + of << "use ieee.std_logic_1164.all;" << std::endl; + for (std::list::const_iterator it = uses_.begin(); it != uses_.end(); ++it) @@ -201,6 +206,20 @@ bool vhdl_arch::have_declared_component(const std::string &name) const return false; } +/* + * True if any declaration of `name' has been added to the + * architecture. + */ +bool vhdl_arch::have_declared(const std::string &name) const +{ + decl_list_t::const_iterator it; + for (it = decls_.begin(); it != decls_.end(); ++it) { + if ((*it)->get_name() == name) + return true; + } + return false; +} + vhdl_arch *vhdl_conc_stmt::get_parent() const { assert(parent_); @@ -337,6 +356,19 @@ void vhdl_var_decl::emit(std::ofstream &of, int level) const emit_comment(of, level, true); } +vhdl_signal_decl::~vhdl_signal_decl() +{ + delete type_; +} + +void vhdl_signal_decl::emit(std::ofstream &of, int level) const +{ + of << "signal " << name_ << " : "; + type_->emit(of, level); + of << ";"; + emit_comment(of, level, true); +} + void vhdl_expr_list::add_expr(vhdl_expr *e) { exprs_.push_back(e); diff --git a/tgt-vhdl/vhdl_element.hh b/tgt-vhdl/vhdl_element.hh index 76e475d3a..3498fead3 100644 --- a/tgt-vhdl/vhdl_element.hh +++ b/tgt-vhdl/vhdl_element.hh @@ -220,6 +220,21 @@ private: }; +/* + * A signal declaration in architecture. + */ +class vhdl_signal_decl : public vhdl_decl { +public: + vhdl_signal_decl(const char *name, vhdl_type *type) + : vhdl_decl(name), type_(type) {} + ~vhdl_signal_decl(); + + void emit(std::ofstream &of, int level) const; +private: + vhdl_type *type_; +}; + + /* * Instantiation of component. This is really only a placeholder * at the moment until the port mappings are worked out. @@ -269,6 +284,7 @@ public: void emit(std::ofstream &of, int level=0) const; bool have_declared_component(const std::string &name) const; + bool have_declared(const std::string &name) const; void add_decl(vhdl_decl *decl); void add_stmt(vhdl_conc_stmt *stmt); vhdl_entity *get_parent() const; @@ -295,7 +311,7 @@ public: vhdl_arch *get_arch() const { return arch_; } const std::string &get_name() const { return name_; } void requires_package(const char *spec); - const std::string &get_derived_from() const { return derived_from_; } + const std::string &get_derived_from() const { return derived_from_; } private: std::string name_; vhdl_arch *arch_; // Entity may only have a single architecture