vpi: implement extended VCD ($dumpports) writer
Implement the IEEE 1364-2005 Clause 18 extended VCD task family ($dumpports / $dumpportsall / $dumpportsoff / $dumpportson / $dumpportsflush / $dumpportslimit), which were previously registered as "not implemented" stubs. The new vpi/sys_evcd.c reaches each port's value-bearing net through the port's vpiLowConn relationship and reads per-bit drive strength with vpiStrengthVal, emitting $var port declarations and p-records (per-bit state character plus strength0/strength1 components). Scalar and vector ports are supported; the initial checkpoint is deferred to the read-only synch so it records settled values. The encoding is byte-compatible with the GHDL --evcd writer so one waveform reader works across Verilog and VHDL. To resolve a port to its net, the VPI is completed: vpiLowConn and vpiHighConn are now implemented on vpiPortInfo. tgt-vvp emits the port's low (formal) and high (actual) net symbols in the .port_info directive, the vvp assembler parses them (compile_port_info), and vpiPortInfo resolves each to the __vpiSignal sharing that net. New vpi_user.h constants vpiHighConn (135) and vpiLowConn (136) use iverilog's private numbering to avoid colliding with vpiArgument/vpiBit. Tests: ivtest evcd_basic (scalar in/out/inout), evcd_bus (vector ports) and evcd_onoff ($dumpportsoff/on/all), each gold-diffed. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
William P. Moore
parent
de415b2f03
commit
96cf1674a4
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@ -126,3 +126,29 @@ Compile, run, and view waveforms with GTKWave using these commands:
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Click on the 'test', then 'c1' in the top left box of GTKWave, then drag the
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signals to the Signals box. You will be able to add signals to display,
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scanning by scope.
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Extended VCD (port dumps)
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-------------------------
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In addition to the four-state VCD produced by $dumpvars, Icarus Verilog can
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write an *extended* VCD file (IEEE 1364-2005 Clause 18) that records the
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ports of one or more module instances together with their direction and drive
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strength. This is enabled with the $dumpports system task instead of
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$dumpfile/$dumpvars:
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.. code-block:: verilog
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initial
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begin
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$dumpports(dut_instance, "ports.evcd");
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end
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Each port is written with a ``$var port`` declaration and its value changes are
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recorded as ``p`` records carrying a per-bit state character (input ``D``/``U``,
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output ``L``/``H``, three-state, etc.) and the strength0/strength1 components.
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The companion tasks $dumpportsall, $dumpportsoff, $dumpportson,
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$dumpportsflush, and $dumpportslimit mirror the corresponding $dumpall family.
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The extended VCD format is byte-compatible with the GHDL ``--evcd`` writer, so
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the same waveform reader can consume port dumps from both Verilog and VHDL
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designs.
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@ -0,0 +1,35 @@
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$date
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Fri Jun 19 15:35:19 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module evcd_basic.u $end
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$var port 1 <0 a $end
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$var port 1 <1 b $end
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$var port 1 <2 y $end
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$var port 1 <3 io $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpports
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pD 6 0 <0
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pD 6 0 <1
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pL 6 0 <2
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pF 0 0 <3
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$end
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#5
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pU 0 6 <0
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p0 6 0 <3
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#10
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pU 0 6 <1
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p1 0 6 <3
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pH 0 6 <2
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#15
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pD 6 0 <0
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pF 0 0 <3
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pL 6 0 <2
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#20
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@ -0,0 +1,29 @@
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$date
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Fri Jun 19 15:35:20 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module evcd_bus.u $end
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$var port [3:0] <0 din $end
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$var port [3:0] <1 dout $end
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$var port [3:0] <2 bus $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpports
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pDDDD 6666 0000 <0
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pHHHH 0000 6666 <1
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pFFFF 0000 0000 <2
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$end
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#5
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pUDUD 0606 6060 <0
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pLHLH 6060 0606 <1
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#10
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pUUUU 0000 6666 <0
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pLLLL 6666 0000 <1
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p1111 0000 6666 <2
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#15
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@ -0,0 +1,47 @@
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$date
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Fri Jun 19 15:35:20 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module evcd_onoff.u $end
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$var port 1 <0 clk $end
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$var port 1 <1 d $end
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$var port 1 <2 q $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpports
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pD 6 0 <0
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pD 6 0 <1
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pX 6 6 <2
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$end
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#5
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pU 0 6 <0
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pL 6 0 <2
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#7
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pU 0 6 <1
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#10
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pD 6 0 <0
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#13
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pN 6 6 <0
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pN 6 6 <1
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pX 6 6 <2
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#25
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pU 0 6 <0
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pD 6 0 <1
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pH 0 6 <2
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pL 6 0 <2
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#30
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pD 6 0 <0
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#35
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pD 6 0 <0
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pD 6 0 <1
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pL 6 0 <2
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pU 0 6 <0
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#40
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pD 6 0 <0
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#40
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@ -0,0 +1,20 @@
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// Extended VCD ($dumpports): scalar input / output / inout ports.
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module evcd_basic_dut (input wire a, input wire b,
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output wire y, inout wire io);
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assign y = a & b;
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assign io = a ? b : 1'bz;
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endmodule
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module evcd_basic;
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reg a, b;
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wire y, io;
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evcd_basic_dut u (.a(a), .b(b), .y(y), .io(io));
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initial begin
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$dumpports(u, "work/evcd_basic.evcd");
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a = 1'b0; b = 1'b0; #5;
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a = 1'b1; b = 1'b0; #5;
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a = 1'b1; b = 1'b1; #5;
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a = 1'b0; b = 1'b1; #5;
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$finish;
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end
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endmodule
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@ -0,0 +1,19 @@
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// Extended VCD ($dumpports): vector (bus) input / output / inout ports.
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module evcd_bus_dut (input wire [3:0] din, output wire [3:0] dout,
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inout wire [3:0] bus);
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assign dout = ~din;
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assign bus = din[0] ? din : 4'bzzzz;
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endmodule
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module evcd_bus;
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reg [3:0] din;
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wire [3:0] dout, bus;
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evcd_bus_dut u (.din(din), .dout(dout), .bus(bus));
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initial begin
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$dumpports(u, "work/evcd_bus.evcd");
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din = 4'b0000; #5;
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din = 4'b1010; #5;
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din = 4'b1111; #5;
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$finish;
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end
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endmodule
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@ -0,0 +1,24 @@
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// Extended VCD: $dumpportsoff suspends (X checkpoint), $dumpportson resumes,
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// $dumpportsall forces a checkpoint.
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module evcd_onoff_dut (input wire clk, input wire d, output wire q);
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reg r;
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assign q = r;
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always @(posedge clk) r <= d;
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endmodule
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module evcd_onoff;
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reg clk, d;
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wire q;
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evcd_onoff_dut u (.clk(clk), .d(d), .q(q));
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always #5 clk = ~clk;
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initial begin
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$dumpports(u, "work/evcd_onoff.evcd");
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clk = 0; d = 0;
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#7 d = 1;
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#6 $dumpportsoff;
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#10 d = 0;
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#2 $dumpportson;
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#10 $dumpportsall;
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#5 $finish;
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end
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endmodule
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@ -515,6 +515,9 @@ drive_strength3 normal ivltests
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dummy7 normal ivltests gold=dummy7.gold
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dump_memword normal ivltests diff=work/test.vcd:gold/dump_memword.vcd:2
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dumpvars normal ivltests # PR#174: dumpvars non-hierarchical arguments
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evcd_basic normal ivltests diff=work/evcd_basic.evcd:gold/evcd_basic.evcd.gold:2
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evcd_bus normal ivltests diff=work/evcd_bus.evcd:gold/evcd_bus.evcd.gold:2
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evcd_onoff normal ivltests diff=work/evcd_onoff.evcd:gold/evcd_onoff.evcd.gold:2
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eeq normal ivltests # === and !== in structural context
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else1 normal ivltests # ifdef with else
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else2 normal ivltests # compound ifdef with else
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@ -2321,6 +2321,69 @@ static const char *vvp_port_info_type_str(ivl_signal_port_t ptype)
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}
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}
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/* Emit the low (inner/formal) and, when present, high (outer/actual)
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connection nets of a module port into a .port_info record, so that VPI
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consumers can reach them via vpiLowConn / vpiHighConn. The two nets are
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the signals that share the port's nexus in the module's own scope and
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in the instantiating (parent) scope respectively. */
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static void emit_mod_port_conns(ivl_scope_t mod, unsigned idx, const char*pname)
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{
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ivl_net_logic_t buffer = ivl_scope_mod_module_port_buffer(mod, idx);
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ivl_scope_t parent = ivl_scope_parent(mod);
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ivl_nexus_t port_nex = ivl_scope_mod_port(mod, idx);
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ivl_signal_t inner = 0, outer = 0;
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unsigned sigs, si;
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int have_low = 0;
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/* The formal (inner) signal is the port signal of this scope with
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the port's name. Its nexus is shared with the actual net in the
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instantiating scope (the same collapsing the netlist uses for
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port connections), so the high connection is found there. */
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sigs = ivl_scope_sigs(mod);
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for (si = 0 ; si < sigs ; si += 1) {
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ivl_signal_t s = ivl_scope_sig(mod, si);
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if (ivl_signal_port(s) == IVL_SIP_NONE)
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continue;
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if (pname && strcmp(ivl_signal_basename(s), pname) == 0) {
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inner = s;
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break;
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}
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}
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if (inner) {
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ivl_nexus_t nex = ivl_signal_nex(inner, 0);
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if (nex) {
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unsigned k, np = ivl_nexus_ptrs(nex);
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for (k = 0 ; k < np ; k += 1) {
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ivl_signal_t s = ivl_nexus_ptr_sig(ivl_nexus_ptr(nex, k));
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if (s && parent && ivl_signal_scope(s) == parent) {
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outer = s;
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break;
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}
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}
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}
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}
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/* Low (inner) connection: prefer an explicit port buffer, then the
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formal signal, then any signal on the module-port nexus. */
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if (buffer) {
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fprintf(vvp_out, " L_%p", buffer);
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have_low = 1;
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} else if (inner) {
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fprintf(vvp_out, " v%p_0", (void*)inner);
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have_low = 1;
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} else if (port_nex) {
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fprintf(vvp_out, " %s", draw_input_from_net(port_nex));
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have_low = 1;
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}
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/* High (outer) connection, only meaningful alongside a low one. */
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if (have_low && outer)
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fprintf(vvp_out, " v%p_0", (void*)outer);
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fprintf(vvp_out, ";\n");
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}
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int draw_scope(ivl_scope_t net, ivl_scope_t parent)
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{
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unsigned idx;
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@ -2401,14 +2464,15 @@ int draw_scope(ivl_scope_t net, ivl_scope_t parent)
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const char *name = ivl_scope_mod_module_port_name(net,idx);
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ivl_signal_port_t ptype = ivl_scope_mod_module_port_type(net,idx);
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unsigned width = ivl_scope_mod_module_port_width(net,idx);
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ivl_net_logic_t buffer = ivl_scope_mod_module_port_buffer(net,idx);
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if( name == 0 )
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name = "";
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fprintf( vvp_out, " .port_info %u %s %u \"%s\"",
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idx, vvp_port_info_type_str(ptype), width,
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vvp_mangle_name(name) );
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if (buffer) fprintf( vvp_out, " L_%p;\n", buffer);
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else fprintf( vvp_out, ";\n");
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/* Emit the port's low (formal, inside) and high (actual,
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outside) connection nets so VPI consumers can reach them
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via vpiLowConn / vpiHighConn. */
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emit_mod_port_conns(net, idx, name);
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}
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}
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@ -57,7 +57,7 @@ O = sys_table.o sys_convert.o sys_countdrivers.o sys_darray.o sys_deposit.o \
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sys_display.o \
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sys_fileio.o sys_finish.o sys_icarus.o sys_plusargs.o sys_queue.o \
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sys_random.o sys_random_mti.o sys_readmem.o sys_readmem_lex.o sys_scanf.o \
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sys_sdf.o sys_time.o sys_vcd.o sys_vcdoff.o vcd_priv.o mt19937int.o \
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sys_sdf.o sys_time.o sys_vcd.o sys_evcd.o sys_vcdoff.o vcd_priv.o mt19937int.o \
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sys_priv.o sdf_parse.o sdf_lexor.o stringheap.o vams_simparam.o \
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table_mod.o table_mod_parse.o table_mod_lexor.o
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OPP = vcd_priv2.o
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@ -0,0 +1,492 @@
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/*
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* Copyright (c) 2026 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "sys_priv.h"
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/*
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* This file implements the IEEE 1364-2005 Clause 18 Extended VCD
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* ($dumpports) task family. The port direction comes from the vpiPort
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* (vpiPortInfo) meta-data; the value-bearing net is reached through the
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* port's vpiLowConn relationship, and its per-bit drive strength is read
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* with vpiStrengthVal. The output is byte-compatible (for scalar ports)
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* with the GHDL --evcd writer so a single waveform reader works across
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* Verilog and VHDL.
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*
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* PHASE 1: scalar (1-bit) input/output/inout ports -- full pipeline
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* (header, $scope/$var/$upscope, initial checkpoint, value changes).
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* Vector ports are declared with their range but only bit 0 is dumped;
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* the full bus encoding is pinned against the GHDL reference in Phase 2.
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*/
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# include <stdio.h>
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# include <stdlib.h>
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# include <string.h>
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# include <assert.h>
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# include <time.h>
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# include "ivl_alloc.h"
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static FILE *evcd_file = NULL;
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static int evcd_no_date = 0;
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static PLI_UINT64 evcd_cur_time = 0;
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static int evcd_time_set = 0;
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static int evcd_is_off = 0;
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static int evcd_started = 0; /* initial checkpoint emitted yet? */
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static const char*units_names[] = { "s", "ms", "us", "ns", "ps", "fs" };
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/* One tracked port. */
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struct evcd_port {
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vpiHandle net; /* value net (vpiLowConn of the port) */
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int dir; /* vpiInput / vpiOutput / vpiInout */
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unsigned width;
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int id; /* EVCD identifier integer */
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struct evcd_port*next;
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};
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static struct evcd_port*evcd_list = NULL;
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static struct evcd_port*evcd_tail = NULL; /* append here to keep id order */
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static int evcd_next_id = 0;
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/* ------------------------------------------------------------------ */
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/* State-char and strength mapping (GHDL byte-compatible) */
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/* ------------------------------------------------------------------ */
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/* Map a 4-state logic value (vpi0/vpi1/vpiZ/vpiX, with vpiH/vpiL folded
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onto 1/0) and a port direction to the EVCD state character. */
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static char evcd_state_char(int logic, int dir)
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{
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int v; /* 0, 1, 2=Z, 3=X */
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switch (logic) {
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case vpi0: case vpiL: v = 0; break;
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case vpi1: case vpiH: v = 1; break;
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case vpiZ: v = 2; break;
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default: v = 3; break;
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}
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if (dir == vpiInput) {
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switch (v) { case 0: return 'D'; case 1: return 'U';
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case 2: return 'Z'; default: return 'N'; }
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} else if (dir == vpiOutput) {
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switch (v) { case 0: return 'L'; case 1: return 'H';
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case 2: return 'T'; default: return 'X'; }
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} else { /* inout / unknown direction */
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switch (v) { case 0: return '0'; case 1: return '1';
|
||||
case 2: return 'F'; default: return '?'; }
|
||||
}
|
||||
}
|
||||
|
||||
/* The strength0 / strength1 components for a value, using the
|
||||
GHDL-compatible convention: a driven level is strong (6), the opposite
|
||||
rail is high-Z (0); three-state is 0/0; unknown is 6/6. */
|
||||
static void evcd_strengths(int logic, int*s0, int*s1)
|
||||
{
|
||||
switch (logic) {
|
||||
case vpi0: case vpiL: *s0 = 6; *s1 = 0; break;
|
||||
case vpi1: case vpiH: *s0 = 0; *s1 = 6; break;
|
||||
case vpiZ: *s0 = 0; *s1 = 0; break;
|
||||
default: *s0 = 6; *s1 = 6; break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Emit one value record for a port:
|
||||
|
||||
scalar -> p<state> <s0> <s1> <<id>
|
||||
vector -> p<state...> <s0...> <s1...> <<id>
|
||||
|
||||
For an N-bit port the state and each strength component carry N
|
||||
characters, most-significant bit first (matching the [msb:lsb] $var
|
||||
declaration), and the encoding is byte-compatible with GHDL --evcd. */
|
||||
static void evcd_emit_value(struct evcd_port*p)
|
||||
{
|
||||
s_vpi_value val;
|
||||
int logic, s0, s1, idx;
|
||||
|
||||
val.format = vpiStrengthVal;
|
||||
vpi_get_value(p->net, &val);
|
||||
|
||||
if (p->width <= 1) {
|
||||
logic = (int)val.value.strength[0].logic;
|
||||
evcd_strengths(logic, &s0, &s1);
|
||||
fprintf(evcd_file, "p%c %d %d <%d\n",
|
||||
evcd_state_char(logic, p->dir), s0, s1, p->id);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Bit 0 of the strength array is the LSB; emit MSB first. */
|
||||
fputc('p', evcd_file);
|
||||
for (idx = (int)p->width - 1 ; idx >= 0 ; idx -= 1)
|
||||
fputc(evcd_state_char((int)val.value.strength[idx].logic, p->dir),
|
||||
evcd_file);
|
||||
fputc(' ', evcd_file);
|
||||
for (idx = (int)p->width - 1 ; idx >= 0 ; idx -= 1) {
|
||||
evcd_strengths((int)val.value.strength[idx].logic, &s0, &s1);
|
||||
fputc('0' + s0, evcd_file);
|
||||
}
|
||||
fputc(' ', evcd_file);
|
||||
for (idx = (int)p->width - 1 ; idx >= 0 ; idx -= 1) {
|
||||
evcd_strengths((int)val.value.strength[idx].logic, &s0, &s1);
|
||||
fputc('0' + s1, evcd_file);
|
||||
}
|
||||
fprintf(evcd_file, " <%d\n", p->id);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------ */
|
||||
/* Time + value-change callback */
|
||||
/* ------------------------------------------------------------------ */
|
||||
|
||||
static PLI_UINT64 evcd_now(void)
|
||||
{
|
||||
s_vpi_time now;
|
||||
now.type = vpiSimTime;
|
||||
vpi_get_time(0, &now);
|
||||
return ((PLI_UINT64)now.high << 32) | (PLI_UINT64)now.low;
|
||||
}
|
||||
|
||||
static void evcd_emit_time(PLI_UINT64 t)
|
||||
{
|
||||
if (!evcd_time_set || t != evcd_cur_time) {
|
||||
fprintf(evcd_file, "#%" PLI_UINT64_FMT "\n", t);
|
||||
evcd_cur_time = t;
|
||||
evcd_time_set = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static PLI_INT32 evcd_value_cb(struct t_cb_data*cb)
|
||||
{
|
||||
struct evcd_port*p = (struct evcd_port*)cb->user_data;
|
||||
/* Value changes while the design settles at the start time are
|
||||
folded into the initial checkpoint, so ignore them until it has
|
||||
been emitted (at the read-only synch of the current step). */
|
||||
if (evcd_file == NULL || evcd_is_off || !evcd_started)
|
||||
return 0;
|
||||
evcd_emit_time(evcd_now());
|
||||
evcd_emit_value(p);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------ */
|
||||
/* Header */
|
||||
/* ------------------------------------------------------------------ */
|
||||
|
||||
static void evcd_emit_header(void)
|
||||
{
|
||||
int prec = vpi_get(vpiTimePrecision, 0);
|
||||
unsigned scale = 1, udx = 0;
|
||||
time_t walltime;
|
||||
|
||||
time(&walltime);
|
||||
assert(prec >= -15);
|
||||
while (prec < 0) { udx += 1; prec += 3; }
|
||||
while (prec > 0) { scale *= 10; prec -= 1; }
|
||||
|
||||
if (!evcd_no_date) {
|
||||
fprintf(evcd_file, "$date\n\t%s$end\n",
|
||||
asctime(localtime(&walltime)));
|
||||
}
|
||||
fprintf(evcd_file, "$version\n\tIcarus Verilog\n$end\n");
|
||||
fprintf(evcd_file, "$timescale\n\t%u%s\n$end\n", scale, units_names[udx]);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------ */
|
||||
/* Scope / port scan */
|
||||
/* ------------------------------------------------------------------ */
|
||||
|
||||
static const char*evcd_dir_name(int dir)
|
||||
{
|
||||
switch (dir) {
|
||||
case vpiInput: return "input";
|
||||
case vpiOutput: return "output";
|
||||
case vpiInout: return "inout";
|
||||
default: return "?";
|
||||
}
|
||||
}
|
||||
|
||||
/* Declare every port of one module instance scope: emit its $var record,
|
||||
track it, and register a value-change callback on its net. */
|
||||
static void evcd_scan_scope(vpiHandle scope)
|
||||
{
|
||||
vpiHandle ports, port;
|
||||
|
||||
fprintf(evcd_file, "$scope module %s $end\n",
|
||||
vpi_get_str(vpiFullName, scope));
|
||||
|
||||
ports = vpi_iterate(vpiPort, scope);
|
||||
while (ports && (port = vpi_scan(ports))) {
|
||||
struct evcd_port*p;
|
||||
s_cb_data cb;
|
||||
s_vpi_time tm;
|
||||
const char*name = vpi_get_str(vpiName, port);
|
||||
int dir = vpi_get(vpiDirection, port);
|
||||
unsigned width = vpi_get(vpiSize, port);
|
||||
vpiHandle net = vpi_handle(vpiLowConn, port);
|
||||
|
||||
if (net == NULL) {
|
||||
vpi_printf("EVCD warning: port %s has no value net; "
|
||||
"skipping.\n", name ? name : "?");
|
||||
continue;
|
||||
}
|
||||
|
||||
p = (struct evcd_port*)calloc(1, sizeof *p);
|
||||
p->net = net;
|
||||
p->dir = dir;
|
||||
p->width = width;
|
||||
p->id = evcd_next_id++;
|
||||
p->next = NULL;
|
||||
/* Append so checkpoints emit records in ascending id order
|
||||
(matching the GHDL --evcd writer). */
|
||||
if (evcd_tail) evcd_tail->next = p;
|
||||
else evcd_list = p;
|
||||
evcd_tail = p;
|
||||
|
||||
/* $var port <size> <<id> <reference> $end. Use the port's
|
||||
actual declared [msb:lsb] range when it is a vector. */
|
||||
if (width > 1 || vpi_get(vpiLeftRange, net) != 0)
|
||||
fprintf(evcd_file, "$var port [%d:%d] <%d %s $end\n",
|
||||
(int)vpi_get(vpiLeftRange, net),
|
||||
(int)vpi_get(vpiRightRange, net), p->id, name);
|
||||
else
|
||||
fprintf(evcd_file, "$var port 1 <%d %s $end\n", p->id, name);
|
||||
|
||||
/* Track value changes on the port's value net. */
|
||||
memset(&cb, 0, sizeof cb);
|
||||
tm.type = vpiSimTime;
|
||||
cb.reason = cbValueChange;
|
||||
cb.cb_rtn = evcd_value_cb;
|
||||
cb.obj = net;
|
||||
cb.time = &tm;
|
||||
cb.value = NULL;
|
||||
cb.user_data = (PLI_BYTE8*)p;
|
||||
vpi_register_cb(&cb);
|
||||
|
||||
(void)evcd_dir_name; /* reserved for diagnostics */
|
||||
}
|
||||
|
||||
fprintf(evcd_file, "$upscope $end\n");
|
||||
}
|
||||
|
||||
/* Dump the current value of every tracked port (checkpoint). */
|
||||
static void evcd_checkpoint(void)
|
||||
{
|
||||
struct evcd_port*p;
|
||||
for (p = evcd_list ; p ; p = p->next)
|
||||
evcd_emit_value(p);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------ */
|
||||
/* End of simulation */
|
||||
/* ------------------------------------------------------------------ */
|
||||
|
||||
static PLI_INT32 evcd_end_cb(struct t_cb_data*cb)
|
||||
{
|
||||
(void)cb;
|
||||
if (evcd_file) {
|
||||
fprintf(evcd_file, "#%" PLI_UINT64_FMT "\n", evcd_now());
|
||||
fflush(evcd_file);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* The initial checkpoint, deferred to the read-only synch of the start
|
||||
time so it records settled values: #<t> $dumpports <values> $end. */
|
||||
static PLI_INT32 evcd_initial_cb(struct t_cb_data*cb)
|
||||
{
|
||||
(void)cb;
|
||||
if (evcd_file == NULL)
|
||||
return 0;
|
||||
evcd_cur_time = evcd_now();
|
||||
evcd_time_set = 1;
|
||||
fprintf(evcd_file, "#%" PLI_UINT64_FMT "\n$dumpports\n", evcd_cur_time);
|
||||
evcd_checkpoint();
|
||||
fprintf(evcd_file, "$end\n");
|
||||
evcd_started = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------ */
|
||||
/* $dumpports */
|
||||
/* ------------------------------------------------------------------ */
|
||||
|
||||
static PLI_INT32 sys_dumpports_calltf(ICARUS_VPI_CONST PLI_BYTE8*name)
|
||||
{
|
||||
vpiHandle systf, argv, arg;
|
||||
vpiHandle scopes[64];
|
||||
unsigned nscopes = 0;
|
||||
char*path = NULL;
|
||||
s_cb_data cb;
|
||||
unsigned i;
|
||||
(void)name;
|
||||
|
||||
if (evcd_file != NULL) {
|
||||
vpi_printf("EVCD warning: $dumpports already active; ignored.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
systf = vpi_handle(vpiSysTfCall, 0);
|
||||
argv = vpi_iterate(vpiArgument, systf);
|
||||
|
||||
/* Arguments are module instances to dump plus, optionally, a
|
||||
trailing file name (string). Anything that is not a module is
|
||||
treated as the file-name expression. */
|
||||
while (argv && (arg = vpi_scan(argv))) {
|
||||
if (vpi_get(vpiType, arg) == vpiModule) {
|
||||
if (nscopes < 64)
|
||||
scopes[nscopes++] = arg;
|
||||
} else if (path == NULL) {
|
||||
s_vpi_value v;
|
||||
v.format = vpiStringVal;
|
||||
vpi_get_value(arg, &v);
|
||||
if (v.value.str && v.value.str[0])
|
||||
path = strdup(v.value.str);
|
||||
}
|
||||
}
|
||||
|
||||
/* Default scope = the module containing the call; default file. */
|
||||
if (nscopes == 0) {
|
||||
vpiHandle sc = vpi_handle(vpiScope, systf);
|
||||
if (sc) scopes[nscopes++] = sc;
|
||||
}
|
||||
if (path == NULL)
|
||||
path = strdup("dumpports.vcd");
|
||||
|
||||
evcd_file = fopen(path, "w");
|
||||
if (evcd_file == NULL) {
|
||||
vpi_printf("EVCD error: cannot open %s for output.\n", path);
|
||||
free(path);
|
||||
return 0;
|
||||
}
|
||||
vpi_printf("EVCD info: dumpports file %s opened for output.\n", path);
|
||||
free(path);
|
||||
|
||||
evcd_emit_header();
|
||||
for (i = 0 ; i < nscopes ; i += 1)
|
||||
evcd_scan_scope(scopes[i]);
|
||||
fprintf(evcd_file, "$enddefinitions $end\n");
|
||||
|
||||
/* Defer the initial checkpoint to the read-only synch of the
|
||||
current time so it captures settled values. */
|
||||
{
|
||||
s_vpi_time tm;
|
||||
tm.type = vpiSimTime;
|
||||
tm.high = 0;
|
||||
tm.low = 0;
|
||||
memset(&cb, 0, sizeof cb);
|
||||
cb.reason = cbReadOnlySynch;
|
||||
cb.cb_rtn = evcd_initial_cb;
|
||||
cb.time = &tm;
|
||||
cb.obj = NULL;
|
||||
vpi_register_cb(&cb);
|
||||
}
|
||||
|
||||
/* Close the file cleanly at the end of simulation. */
|
||||
memset(&cb, 0, sizeof cb);
|
||||
cb.reason = cbEndOfSimulation;
|
||||
cb.cb_rtn = evcd_end_cb;
|
||||
cb.obj = NULL;
|
||||
vpi_register_cb(&cb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* $dumpportsall: force a checkpoint of all port values now. */
|
||||
static PLI_INT32 sys_dumpportsall_calltf(ICARUS_VPI_CONST PLI_BYTE8*name)
|
||||
{
|
||||
(void)name;
|
||||
if (evcd_file == NULL) return 0;
|
||||
evcd_emit_time(evcd_now());
|
||||
evcd_checkpoint();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* $dumpportsoff / $dumpportson: suspend / resume dumping. */
|
||||
static PLI_INT32 sys_dumpportsoff_calltf(ICARUS_VPI_CONST PLI_BYTE8*name)
|
||||
{
|
||||
struct evcd_port*p;
|
||||
(void)name;
|
||||
if (evcd_file == NULL || evcd_is_off) return 0;
|
||||
evcd_emit_time(evcd_now());
|
||||
/* Checkpoint every bit of every port as X while suspended. */
|
||||
for (p = evcd_list ; p ; p = p->next) {
|
||||
int s0, s1;
|
||||
unsigned b;
|
||||
char c = evcd_state_char(vpiX, p->dir);
|
||||
evcd_strengths(vpiX, &s0, &s1);
|
||||
fputc('p', evcd_file);
|
||||
for (b = 0 ; b < p->width ; b += 1) fputc(c, evcd_file);
|
||||
fputc(' ', evcd_file);
|
||||
for (b = 0 ; b < p->width ; b += 1) fputc('0' + s0, evcd_file);
|
||||
fputc(' ', evcd_file);
|
||||
for (b = 0 ; b < p->width ; b += 1) fputc('0' + s1, evcd_file);
|
||||
fprintf(evcd_file, " <%d\n", p->id);
|
||||
}
|
||||
evcd_is_off = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static PLI_INT32 sys_dumpportson_calltf(ICARUS_VPI_CONST PLI_BYTE8*name)
|
||||
{
|
||||
(void)name;
|
||||
if (evcd_file == NULL || !evcd_is_off) return 0;
|
||||
evcd_is_off = 0;
|
||||
evcd_emit_time(evcd_now());
|
||||
evcd_checkpoint();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* $dumpportsflush: flush the output buffer. */
|
||||
static PLI_INT32 sys_dumpportsflush_calltf(ICARUS_VPI_CONST PLI_BYTE8*name)
|
||||
{
|
||||
(void)name;
|
||||
if (evcd_file) fflush(evcd_file);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* $dumpportslimit(size [, file]): accepted for compatibility. The
|
||||
file-size cap is not enforced in Phase 1. */
|
||||
static PLI_INT32 sys_dumpportslimit_calltf(ICARUS_VPI_CONST PLI_BYTE8*name)
|
||||
{
|
||||
(void)name;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------ */
|
||||
/* Registration */
|
||||
/* ------------------------------------------------------------------ */
|
||||
|
||||
static void register_evcd_task(const char*tfname,
|
||||
PLI_INT32 (*calltf)(ICARUS_VPI_CONST PLI_BYTE8*))
|
||||
{
|
||||
s_vpi_systf_data tf;
|
||||
memset(&tf, 0, sizeof tf);
|
||||
tf.type = vpiSysTask;
|
||||
tf.tfname = (PLI_BYTE8*)tfname;
|
||||
tf.calltf = calltf;
|
||||
tf.compiletf = NULL;
|
||||
tf.sizetf = NULL;
|
||||
tf.user_data = (PLI_BYTE8*)tfname;
|
||||
vpi_register_systf(&tf);
|
||||
}
|
||||
|
||||
void sys_evcd_register(void)
|
||||
{
|
||||
register_evcd_task("$dumpports", sys_dumpports_calltf);
|
||||
register_evcd_task("$dumpportsall", sys_dumpportsall_calltf);
|
||||
register_evcd_task("$dumpportsoff", sys_dumpportsoff_calltf);
|
||||
register_evcd_task("$dumpportson", sys_dumpportson_calltf);
|
||||
register_evcd_task("$dumpportsflush", sys_dumpportsflush_calltf);
|
||||
register_evcd_task("$dumpportslimit", sys_dumpportslimit_calltf);
|
||||
}
|
||||
|
|
@ -172,35 +172,8 @@ void sys_special_register(void)
|
|||
res = vpi_register_systf(&tf_data);
|
||||
vpip_make_systf_system_defined(res);
|
||||
|
||||
tf_data.tfname = "$dumpports";
|
||||
tf_data.user_data = "$dumpports";
|
||||
res = vpi_register_systf(&tf_data);
|
||||
vpip_make_systf_system_defined(res);
|
||||
|
||||
tf_data.tfname = "$dumpportsoff";
|
||||
tf_data.user_data = "$dumpportsoff";
|
||||
res = vpi_register_systf(&tf_data);
|
||||
vpip_make_systf_system_defined(res);
|
||||
|
||||
tf_data.tfname = "$dumpportson";
|
||||
tf_data.user_data = "$dumpportson";
|
||||
res = vpi_register_systf(&tf_data);
|
||||
vpip_make_systf_system_defined(res);
|
||||
|
||||
tf_data.tfname = "$dumpportsall";
|
||||
tf_data.user_data = "$dumpportsall";
|
||||
res = vpi_register_systf(&tf_data);
|
||||
vpip_make_systf_system_defined(res);
|
||||
|
||||
tf_data.tfname = "$dumpportslimit";
|
||||
tf_data.user_data = "$dumpportslimit";
|
||||
res = vpi_register_systf(&tf_data);
|
||||
vpip_make_systf_system_defined(res);
|
||||
|
||||
tf_data.tfname = "$dumpportsflush";
|
||||
tf_data.user_data = "$dumpportsflush";
|
||||
res = vpi_register_systf(&tf_data);
|
||||
vpip_make_systf_system_defined(res);
|
||||
/* The $dumpports* extended-VCD task family is implemented in
|
||||
sys_evcd.c (registered via sys_evcd_register); no stubs here. */
|
||||
|
||||
/* The following optional system tasks/functions are not implemented
|
||||
* in Icarus Verilog (from Annex C 1364-2005). */
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ extern void sys_scanf_register(void);
|
|||
extern void sys_sdf_register(void);
|
||||
extern void sys_time_register(void);
|
||||
extern void sys_vcd_register(void);
|
||||
extern void sys_evcd_register(void);
|
||||
extern void sys_vcdoff_register(void);
|
||||
extern void sys_special_register(void);
|
||||
extern void table_model_register(void);
|
||||
|
|
@ -214,6 +215,7 @@ void (*vlog_startup_routines[])(void) = {
|
|||
sys_scanf_register,
|
||||
sys_time_register,
|
||||
sys_lxt_or_vcd_register,
|
||||
sys_evcd_register,
|
||||
sys_sdf_register,
|
||||
sys_special_register,
|
||||
table_model_register,
|
||||
|
|
|
|||
|
|
@ -293,6 +293,13 @@ typedef struct t_vpi_delay {
|
|||
#define vpiPathTerm 43
|
||||
#define vpiPort 44
|
||||
#define vpiPortBit 45
|
||||
/* vpiHighConn/vpiLowConn are the IEEE 1364 port-connection relationships.
|
||||
Icarus uses its own constant numbering, so these take the next free
|
||||
values rather than the standard 89/90 (already used here for other
|
||||
relationships). vpiLowConn is the net inside the module (the formal),
|
||||
vpiHighConn the net outside (the actual). */
|
||||
#define vpiHighConn 135
|
||||
#define vpiLowConn 136
|
||||
#define vpiRealVar 47
|
||||
#define vpiReg 48
|
||||
#define vpiRegBit 49
|
||||
|
|
|
|||
|
|
@ -518,7 +518,7 @@ extern void compile_var_queue(char*label, char*name, unsigned size);
|
|||
* nets connected through module ports.
|
||||
*/
|
||||
|
||||
extern void compile_port_info( unsigned index, int vpi_port_type, unsigned width, const char *name, char* buffer );
|
||||
extern void compile_port_info( unsigned index, int vpi_port_type, unsigned width, const char *name, char* buffer, char* buffer_high = nullptr );
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -717,13 +717,18 @@ statement
|
|||
|
||||
/* Port information for scopes... currently this is just meta-data for VPI queries */
|
||||
|
||||
| K_PORT_INFO T_NUMBER port_type T_NUMBER T_STRING T_SYMBOL T_SYMBOL ';'
|
||||
{ compile_port_info( $2 /* port_index */, $3, $4 /* width */,
|
||||
$5 /*&name */, $6 /* low conn */,
|
||||
$7 /* high conn */ ); }
|
||||
|
||||
| K_PORT_INFO T_NUMBER port_type T_NUMBER T_STRING T_SYMBOL ';'
|
||||
{ compile_port_info( $2 /* port_index */, $3, $4 /* width */,
|
||||
$5 /*&name */, $6 /* buffer */ ); }
|
||||
$5 /*&name */, $6 /* low conn */ ); }
|
||||
|
||||
| K_PORT_INFO T_NUMBER port_type T_NUMBER T_STRING ';'
|
||||
{ compile_port_info( $2 /* port_index */, $3, $4 /* width */,
|
||||
$5 /*&name */, nullptr /* buffer */ ); }
|
||||
$5 /*&name */, nullptr /* low conn */ ); }
|
||||
|
||||
| K_TIMESCALE T_NUMBER T_NUMBER';'
|
||||
{ compile_timescale($2, $3); }
|
||||
|
|
|
|||
|
|
@ -443,7 +443,8 @@ class vpiPortInfo : public __vpiHandle {
|
|||
int vpi_direction,
|
||||
unsigned width,
|
||||
const char *name,
|
||||
char* buffer );
|
||||
char* buffer,
|
||||
char* buffer_high = nullptr );
|
||||
~vpiPortInfo() override;
|
||||
|
||||
int get_type_code(void) const override { return vpiPort; }
|
||||
|
|
@ -466,7 +467,8 @@ class vpiPortInfo : public __vpiHandle {
|
|||
int direction_;
|
||||
unsigned width_;
|
||||
const char *name_;
|
||||
vvp_net_t *ref_;
|
||||
vvp_net_t *ref_; // low (inner) connection: the formal net
|
||||
vvp_net_t *ref_high_; // high (outer) connection: the actual net
|
||||
};
|
||||
|
||||
class vpiPortBitInfo : public __vpiHandle {
|
||||
|
|
|
|||
|
|
@ -666,7 +666,8 @@ vpiPortInfo::vpiPortInfo( __vpiScope *parent,
|
|||
int vpi_direction,
|
||||
unsigned width,
|
||||
const char *name,
|
||||
char* buffer) :
|
||||
char* buffer,
|
||||
char* buffer_high) :
|
||||
parent_(parent),
|
||||
index_(index),
|
||||
direction_(vpi_direction),
|
||||
|
|
@ -675,6 +676,8 @@ vpiPortInfo::vpiPortInfo( __vpiScope *parent,
|
|||
{
|
||||
if (buffer != nullptr) functor_ref_lookup(&ref_, buffer);
|
||||
else ref_ = nullptr;
|
||||
if (buffer_high != nullptr) functor_ref_lookup(&ref_high_, buffer_high);
|
||||
else ref_high_ = nullptr;
|
||||
}
|
||||
|
||||
vpiPortInfo::~vpiPortInfo()
|
||||
|
|
@ -718,6 +721,24 @@ char *vpiPortInfo::vpi_get_str(int code)
|
|||
}
|
||||
|
||||
|
||||
/* Find the signal handle in `scope` whose underlying net is `net`. This
|
||||
recovers the port-connection signal that a vpiPort's low/high
|
||||
connection refers to, so VPI consumers (e.g. the extended-VCD writer)
|
||||
can read its value and register value-change callbacks. The low
|
||||
connection's signal lives in the module's own scope; the high
|
||||
connection's signal lives in the instantiating (parent) scope. */
|
||||
static vpiHandle port_conn(__vpiScope*scope, vvp_net_t*net)
|
||||
{
|
||||
if (scope == 0 || net == 0)
|
||||
return 0;
|
||||
for (size_t idx = 0 ; idx < scope->intern.size() ; idx += 1) {
|
||||
__vpiSignal*sig = dynamic_cast<__vpiSignal*>(scope->intern[idx]);
|
||||
if (sig && sig->node == net)
|
||||
return sig;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
vpiHandle vpiPortInfo::vpi_handle(int code)
|
||||
{
|
||||
|
||||
|
|
@ -727,6 +748,17 @@ vpiHandle vpiPortInfo::vpi_handle(int code)
|
|||
case vpiScope:
|
||||
case vpiModule:
|
||||
return parent_;
|
||||
case vpiLowConn:
|
||||
// The low (inner) connection of the port is the formal
|
||||
// net inside the module. compile_port_info() resolved that
|
||||
// net into ref_; recover its signal handle by matching the
|
||||
// net against the signals declared in this scope.
|
||||
return port_conn(parent_, ref_);
|
||||
case vpiHighConn:
|
||||
// The high (outer) connection is the actual net in the
|
||||
// instantiating scope (parent_->scope), resolved into
|
||||
// ref_high_. Returns 0 for an unconnected or top-level port.
|
||||
return port_conn(parent_ ? parent_->scope : 0, ref_high_);
|
||||
default :
|
||||
break;
|
||||
}
|
||||
|
|
@ -807,10 +839,10 @@ int vpiPortBitInfo::vpi_get(int code)
|
|||
* code-generators etc. There are no actual nets corresponding to instances of module ports
|
||||
* as elaboration directly connects nets connected through module ports.
|
||||
*/
|
||||
void compile_port_info( unsigned index, int vpi_direction, unsigned width, const char *name, char* buffer )
|
||||
void compile_port_info( unsigned index, int vpi_direction, unsigned width, const char *name, char* buffer, char* buffer_high )
|
||||
{
|
||||
vpiPortInfo* obj = new vpiPortInfo( vpip_peek_current_scope(),
|
||||
index, vpi_direction, width, name, buffer );
|
||||
index, vpi_direction, width, name, buffer, buffer_high );
|
||||
vpip_attach_to_current_scope(obj);
|
||||
|
||||
// Create vpiPortBit objects
|
||||
|
|
|
|||
Loading…
Reference in New Issue