From 91b1759602b73a428cf1fcc5adb2ef5d65061222 Mon Sep 17 00:00:00 2001 From: Cary R Date: Thu, 28 Dec 2023 12:14:10 -0800 Subject: [PATCH] More test version cleanup --- ivtest/README.txt | 8 ++----- ivtest/vlog95_reg.pl | 20 +++++------------ ivtest/vpi/spec_delays.c | 12 ---------- ivtest/vpi_gold/pr723-v10.log | 41 ----------------------------------- ivtest/vpi_reg.pl | 15 +++---------- ivtest/vpi_regress.list | 17 --------------- ivtest/vvp_reg.pl | 10 ++++----- 7 files changed, 15 insertions(+), 108 deletions(-) delete mode 100644 ivtest/vpi_gold/pr723-v10.log diff --git a/ivtest/README.txt b/ivtest/README.txt index c99d767ae..f46bf0ff7 100644 --- a/ivtest/README.txt +++ b/ivtest/README.txt @@ -51,9 +51,7 @@ or if perl is located in /usr/bin ./vpi_reg.pl -All these tests should pass for V11.devel. There are -some expected failures for V10, which are flagged as -Not Implemented +All these tests should pass. The individual test results are found in the vpi_log directory and the gold files are in the vpi_gold @@ -81,9 +79,7 @@ or if perl is located in /usr/bin ./vhdl_reg.pl -The expected output for V0.10.devel and V0.9 is located -in the vhdl_regression_report-devel.txt file. V0.8 does -not support converting Verilog to VHDL. +The tests are expected to pass except for the tri* tests. This script also takes the --suffix= and the --with-valgrind flags described above. diff --git a/ivtest/vlog95_reg.pl b/ivtest/vlog95_reg.pl index 71efe430f..7451686b3 100755 --- a/ivtest/vlog95_reg.pl +++ b/ivtest/vlog95_reg.pl @@ -4,7 +4,7 @@ # # This script is based on code with the following Copyright. # -# Copyright (c) 1999-2020 Guy Hutchison (ghutchis@pacbell.net) +# Copyright (c) 1999-2023 Guy Hutchison (ghutchis@pacbell.net) # # This source code is free software; you can redistribute it # and/or modify it in source code form under the terms of the GNU @@ -49,19 +49,11 @@ if ($#ARGV != -1) { &read_regression_list("regress-fsv.list", $ver, $force_sv, ""); } &read_regression_list("regress-vlog95.list", $ver, $force_sv, ""); - &read_regression_list("regress-v$ver.list", $ver, $force_sv, ""); - &read_regression_list("regress-ivl1.list", $ver, $force_sv, ""); - &read_regression_list("regress-vlg.list", $ver, $force_sv, ""); - &read_regression_list("regress-vams.list", $ver, $force_sv, ""); - if ($ver >= 10) { - &read_regression_list("regress-sv.list", $ver, $force_sv, ""); - &read_regression_list("regress-vhdl.list", $ver, $force_sv, ""); - } - if ($ver == 0.9) { - &read_regression_list("regress-synth.list", $ver, $force_sv, ""); - } else { - &read_regression_list("regress-synth.list", $ver, $force_sv, "-S"); - } + &read_regression_list("regress-ivl1.list", $ver, $force_sv, ""); + &read_regression_list("regress-vlg.list", $ver, $force_sv, ""); + &read_regression_list("regress-sv.list", $ver, $force_sv, ""); + &read_regression_list("regress-vhdl.list", $ver, $force_sv, ""); + &read_regression_list("regress-synth.list", $ver, $force_sv, "-S"); } &execute_regression($suffix, $with_valg); &close_report_file; diff --git a/ivtest/vpi/spec_delays.c b/ivtest/vpi/spec_delays.c index 91afc78f6..b436081e4 100644 --- a/ivtest/vpi/spec_delays.c +++ b/ivtest/vpi/spec_delays.c @@ -80,11 +80,7 @@ static PLI_INT32 dump_specify_calltf(PLI_BYTE8*name) delays.time_type = vpiSimTime; delays.mtm_flag = 0; delays.append_flag = 0; -#ifdef IVERILOG_V10 - delays.plusere_flag = 0; -#else delays.pulsere_flag = 0; -#endif vpi_get_delays(item, &delays); vpi_printf("** (%d,%d,%d, %d,%d,%d, %d,%d,%d, %d,%d,%d)\n", (int)delay_times[0].low, @@ -105,11 +101,7 @@ static PLI_INT32 dump_specify_calltf(PLI_BYTE8*name) delays.time_type = vpiScaledRealTime; delays.mtm_flag = 0; delays.append_flag = 0; -#ifdef IVERILOG_V10 - delays.plusere_flag = 0; -#else delays.pulsere_flag = 0; -#endif vpi_get_delays(item, &delays); vpi_printf("** (%f,%f,%f, %f,%f,%f, %f,%f,%f, %f,%f,%f)\n", delay_times[0].real, @@ -145,11 +137,7 @@ static PLI_INT32 dump_specify_calltf(PLI_BYTE8*name) delays.time_type = vpiScaledRealTime; delays.mtm_flag = 0; delays.append_flag = 0; -#ifdef IVERILOG_V10 - delays.plusere_flag = 0; -#else delays.pulsere_flag = 0; -#endif vpi_get_delays(item, &delays); vpi_printf("** (%f,%f,%f, %f,%f,%f, %f,%f,%f, %f,%f,%f)\n", delay_times[0].real, diff --git a/ivtest/vpi_gold/pr723-v10.log b/ivtest/vpi_gold/pr723-v10.log deleted file mode 100644 index e40780e2c..000000000 --- a/ivtest/vpi_gold/pr723-v10.log +++ /dev/null @@ -1,41 +0,0 @@ -Compiling vpi/pr723.c... -Making pr723.vpi from pr723.o... -Open some files -open MCD returned 00000002 -open MCD returned 00000004 -open MCD returned 00000008 -open MCD returned 00000010 -open FD ('r') returned 80000003 -open FD ('r') returned 80000004 -open FD ('w') returned 80000005 -open FD ('w') returned 80000006 -open FD ('a') returned 80000007 -open FD ('a') returned 80000008 -MCD 01: stdout -MCD 02: /dev/null -MCD 03: /dev/null -MCD 04: /dev/null -MCD 05: /dev/null -FP 00: stdin -FP 01: stdout -FP 02: stderr -FP 03: /dev/null -FP 04: /dev/null -FP 05: /dev/null -FP 06: /dev/null -FP 07: /dev/null -FP 08: /dev/null -write to MCD 1 -write to FD 2 -write to FD 1 -Close some files -WARNING: vpi/pr723.v:48: invalid file descriptor/MCD (0x2) given to $fclose. -WARNING: vpi/pr723.v:49: invalid file descriptor/MCD (0x40000000) given to $fclose. -WARNING: vpi/pr723.v:54: invalid file descriptor/MCD (0x80000003) given to $fclose. -WARNING: vpi/pr723.v:57: invalid file descriptor/MCD (0x81ca1ca0) given to $fclose. -MCD 01: stdout -FP 00: stdin -FP 01: stdout -FP 02: stderr -WARNING: vpi/pr723.v:63: invalid file descriptor/MCD (0x40000000) given to $fdisplay. -WARNING: vpi/pr723.v:64: invalid file descriptor/MCD (0x8000000f) given to $fdisplay. diff --git a/ivtest/vpi_reg.pl b/ivtest/vpi_reg.pl index 1abc6f0b5..e46164219 100755 --- a/ivtest/vpi_reg.pl +++ b/ivtest/vpi_reg.pl @@ -195,13 +195,8 @@ sub execute_regression { } $cmd = $with_valg ? "valgrind --trace-children=yes " : ""; - if ($ver < 11) { - $cmd .= "iverilog$sfx $args{$tname} -o vsim vpi/$tname.v >> " . - "vpi_log/$tname.log 2>&1"; - } else { - $cmd .= "iverilog$sfx $args{$tname} -L . -m $tname -o vsim vpi/$tname.v >> " . - "vpi_log/$tname.log 2>&1"; - } + $cmd .= "iverilog$sfx $args{$tname} -L . -m $tname -o vsim vpi/$tname.v >> " . + "vpi_log/$tname.log 2>&1"; if (system("$cmd")) { print "==> Failed - running iverilog.\n"; $failed++; @@ -210,11 +205,7 @@ sub execute_regression { $cmd = $with_valg ? "valgrind --leak-check=full " . "--show-reachable=yes " : ""; - if ($ver < 11) { - $cmd .= "vvp$sfx -M . -m $tname vsim >> vpi_log/$tname.log 2>&1"; - } else { - $cmd .= "vvp$sfx vsim >> vpi_log/$tname.log 2>&1"; - } + $cmd .= "vvp$sfx vsim >> vpi_log/$tname.log 2>&1"; if (system("$cmd")) { print "==> Failed - running vvp.\n"; $failed++; diff --git a/ivtest/vpi_regress.list b/ivtest/vpi_regress.list index 86d68b047..bbbe858fe 100644 --- a/ivtest/vpi_regress.list +++ b/ivtest/vpi_regress.list @@ -54,23 +54,6 @@ vstd:scopes normal scopes.c scopes-std.log msys2:pr723 NI pr723.c pr723.log -#========== -# V10 exceptions -#========== - -# V10 exceptions -v10:br_gh117 NI br_gh117.c br_gh117.gold -v10:br_ml20191013 NI br_ml20191013.c br_ml20191013.gold -v10:by_index NI by_index.c by_index.gold -v10:pr723 normal pr723.c pr723-v10.log -v10:spec_delays normal,-gspecify spec_delays.c spec_delays.log -DIVERILOG_V10 - - -#========== -# V11 exceptions -#========== - - #========== # The default case. #========== diff --git a/ivtest/vvp_reg.pl b/ivtest/vvp_reg.pl index fe80510b4..3828f360e 100755 --- a/ivtest/vvp_reg.pl +++ b/ivtest/vvp_reg.pl @@ -4,7 +4,7 @@ # # This script is based on code with the following Copyright. # -# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# Copyright (c) 1999-2023 Guy Hutchison (ghutchis@pacbell.net) # # This source code is free software; you can redistribute it # and/or modify it in source code form under the terms of the GNU @@ -53,11 +53,9 @@ if ($#ARGV != -1) { } &read_regression_list("regress-ivl1.list", $ver, $force_sv, ""); &read_regression_list("regress-vlg.list", $ver, $force_sv, ""); - if ($ver >= 10) { - &read_regression_list("regress-sv.list", $ver, $force_sv, ""); - &read_regression_list("regress-vhdl.list", $ver, $force_sv, ""); - } - if ($ver == 0.9 or $force_sv) { + &read_regression_list("regress-sv.list", $ver, $force_sv, ""); + &read_regression_list("regress-vhdl.list", $ver, $force_sv, ""); + if ($force_sv) { &read_regression_list("regress-synth.list", $ver, $force_sv, ""); } else { &read_regression_list("regress-synth.list", $ver, $force_sv, "-S");