Add regression test for Verilog data types on module input ports

Using Verilog data types on module input and inout ports is an error in
Verilog. But in SystemVerilog it is allowed and the port should be a net
with the specified data type.

Check that this is supported.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/module_inout_port_type.v

@@ -0,0 +1,14 @@
+// Check Verilog types on a module inout port. In Verilog this is an error, but
+// in SystemVerilog it is supported
+
+module test (
+  inout reg a,
+  inout time b,
+  inout integer c
+);
+
+  initial begin
+    $display("PASSED");
+  end
+
+endmodule

ivtest/ivltests/module_input_port_type.v

@@ -0,0 +1,14 @@
+// Check Verilog types on a module input port. In Verilog this is an error, but
+// in SystemVerilog it is supported
+
+module test (
+  input reg a,
+  input time b,
+  input integer c
+);
+
+  initial begin
+    $display("PASSED");
+  end
+
+endmodule

ivtest/regress-fsv.list

@@ -77,6 +77,8 @@ br_gh25b		normal			ivltests
 br_gh567		normal			ivltests
 check_constant_3	normal			ivltests
 function4		normal			ivltests
+module_inout_port_type	normal			ivltests
+module_input_port_type	normal			ivltests
 parameter_in_generate1	normal			ivltests
 parameter_no_default	normal			ivltests
 parameter_omit1		normal			ivltests

ivtest/regress-vlg.list

@@ -644,6 +644,8 @@ mixed_width_case	normal			ivltests
 modparam		normal			ivltests top # Override parameter via passed down value
 module3.12A		normal			ivltests main
 module3.12B		normal			ivltests
+module_inout_port_type	CE			ivltests
+module_input_port_type	CE			ivltests
 module_output_port_var1	normal			ivltests
 module_output_port_var2	normal			ivltests
 modulus			normal			ivltests # wire % and reg % operators