From 8a2d4e4fa40cd4f434ca41a8ce28966ce5440eae Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 2 Mar 2022 09:36:07 +0100 Subject: [PATCH] Add regression test for Verilog data types on module input ports Using Verilog data types on module input and inout ports is an error in Verilog. But in SystemVerilog it is allowed and the port should be a net with the specified data type. Check that this is supported. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_inout_port_type.v | 14 ++++++++++++++ ivtest/ivltests/module_input_port_type.v | 14 ++++++++++++++ ivtest/regress-fsv.list | 2 ++ ivtest/regress-vlg.list | 2 ++ 4 files changed, 32 insertions(+) create mode 100644 ivtest/ivltests/module_inout_port_type.v create mode 100644 ivtest/ivltests/module_input_port_type.v diff --git a/ivtest/ivltests/module_inout_port_type.v b/ivtest/ivltests/module_inout_port_type.v new file mode 100644 index 000000000..3c9d2f277 --- /dev/null +++ b/ivtest/ivltests/module_inout_port_type.v @@ -0,0 +1,14 @@ +// Check Verilog types on a module inout port. In Verilog this is an error, but +// in SystemVerilog it is supported + +module test ( + inout reg a, + inout time b, + inout integer c +); + + initial begin + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/module_input_port_type.v b/ivtest/ivltests/module_input_port_type.v new file mode 100644 index 000000000..54dd15c99 --- /dev/null +++ b/ivtest/ivltests/module_input_port_type.v @@ -0,0 +1,14 @@ +// Check Verilog types on a module input port. In Verilog this is an error, but +// in SystemVerilog it is supported + +module test ( + input reg a, + input time b, + input integer c +); + + initial begin + $display("PASSED"); + end + +endmodule diff --git a/ivtest/regress-fsv.list b/ivtest/regress-fsv.list index 2b847a618..d990342fc 100644 --- a/ivtest/regress-fsv.list +++ b/ivtest/regress-fsv.list @@ -77,6 +77,8 @@ br_gh25b normal ivltests br_gh567 normal ivltests check_constant_3 normal ivltests function4 normal ivltests +module_inout_port_type normal ivltests +module_input_port_type normal ivltests parameter_in_generate1 normal ivltests parameter_no_default normal ivltests parameter_omit1 normal ivltests diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index ff022cf10..09d213229 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -644,6 +644,8 @@ mixed_width_case normal ivltests modparam normal ivltests top # Override parameter via passed down value module3.12A normal ivltests main module3.12B normal ivltests +module_inout_port_type CE ivltests +module_input_port_type CE ivltests module_output_port_var1 normal ivltests module_output_port_var2 normal ivltests modulus normal ivltests # wire % and reg % operators