Parse component declarations / parse signal declarations.

These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.

Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.

vhdlpp/Makefile.in

@@ -60,7 +60,8 @@ LIBS = @LIBS@ @EXTRALIBS@
 M = StringHeap.o LineInfo.o
 
 O = main.o architec.o  compiler.o entity.o entity_elaborate.o \
-    expression.o vtype.o lexor.o lexor_keyword.o parse.o parse_misc.o vhdlreal.o vhdlint.o debug.o \
+    expression.o vsignal.o vtype.o lexor.o lexor_keyword.o parse.o \
+    parse_misc.o vhdlreal.o vhdlint.o debug.o \
     architec_emit.o entity_emit.o expression_emit.o \
     $M
 

vhdlpp/architec.cc

@@ -22,9 +22,13 @@
 
 using namespace std;
 
-Architecture::Architecture(perm_string name, list<Architecture::Statement*>&s)
+Architecture::Architecture(perm_string name, map<perm_string,Signal*>&sigs,
+			   map<perm_string,ComponentBase*>&comps,
+			   list<Architecture::Statement*>&s)
 : name_(name)
 {
+      signals_ = sigs;
+      components_ = comps;
       statements_.splice(statements_.end(), s);
 }
 

vhdlpp/architec.h

@@ -22,9 +22,12 @@
 # include  "StringHeap.h"
 # include  "LineInfo.h"
 # include  <list>
+# include  <map>
 
+class ComponentBase;
 class Entity;
 class Expression;
+class Signal;
 
 /*
  * The Architecture class carries the contents (name, statements,
@@ -53,7 +56,9 @@ class Architecture : public LineInfo {
     public:
 	// Create an architecture from its name and its statements.
 	// NOTE: The statement list passed in is emptied.
-      Architecture(perm_string name, std::list<Architecture::Statement*>&s);
+      Architecture(perm_string name, std::map<perm_string,Signal*>&sigs,
+		   std::map<perm_string,ComponentBase*>&comps,
+		   std::list<Architecture::Statement*>&s);
       ~Architecture();
 
       perm_string get_name() const { return name_; }
@@ -69,7 +74,11 @@ class Architecture : public LineInfo {
 
     private:
       perm_string name_;
-
+	// Signals declared local to this architecture
+      std::map<perm_string,Signal*> signals_;
+	// Component declarations...
+      std::map<perm_string,ComponentBase*> components_;
+	// Concurrent statements local to this architecture
       std::list<Architecture::Statement*> statements_;
 
     private: // Not implemented

vhdlpp/debug.cc

@@ -21,6 +21,7 @@
 # include  "entity.h"
 # include  "architec.h"
 # include  "expression.h"
+# include  "vsignal.h"
 # include  "vtype.h"
 # include  <fstream>
 # include  <iomanip>
@@ -54,10 +55,8 @@ void dump_design_entities(const char*path)
       }
 }
 
-void Entity::dump(ostream&out) const
+void ComponentBase::dump_ports(ostream&out) const
 {
-      out << "entity " << name_
-	  << " file=" << get_fileline() << endl;
       if (ports_.size() == 0) {
 	    out << "    No ports" << endl;
       } else {
@@ -75,10 +74,17 @@ void Entity::dump(ostream&out) const
 		  out << ", file=" << item->get_fileline() << endl;
 	    }
       }
+}
+
+void Entity::dump(ostream&out) const
+{
+      out << "entity " << get_name()
+	  << " file=" << get_fileline() << endl;
+      dump_ports(out);
 
       for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin()
 		 ; cur != arch_.end() ; ++cur) {
-	    cur->second->dump(out, name_);
+	    cur->second->dump(out, get_name());
       }
 }
 
@@ -88,6 +94,20 @@ void Architecture::dump(ostream&out, perm_string of_entity) const
 	  << " of entity " << of_entity
 	  << " file=" << get_fileline() << endl;
 
+	// Dump signal declarations
+      for (map<perm_string,Signal*>::const_iterator cur = signals_.begin()
+		 ; cur != signals_.end() ; ++cur) {
+	    cur->second->dump(out);
+      }
+
+	// Dump component declarations
+      for (map<perm_string,ComponentBase*>::const_iterator cur = components_.begin()
+		 ; cur != components_.end() ; ++cur) {
+	    out << "   component " << cur->first << " is" << endl;
+	    cur->second->dump_ports(out);
+	    out << "   end component " << cur->first << endl;
+      }
+
       for (list<Architecture::Statement*>::const_iterator cur = statements_.begin()
 		 ; cur != statements_.end() ; ++cur) {
 	    (*cur)->dump(out);
@@ -99,6 +119,11 @@ void Architecture::Statement::dump(ostream&out) const
       out << "   Architecutre::Statement at file=" << get_fileline() << endl;
 }
 
+void Signal::dump(ostream&out) const
+{
+      out << "   signal " << name_ << " is " << *type_ << endl;
+}
+
 void SignalAssignment::dump(ostream&out) const
 {
       out << "   SignalAssignment file=" << get_fileline() << endl;

vhdlpp/entity.cc

@@ -25,16 +25,16 @@ using namespace std;
 
 std::map<perm_string,Entity*> design_entities;
 
-Entity::Entity(perm_string name)
+ComponentBase::ComponentBase(perm_string name)
 : name_(name)
 {
 }
 
-Entity::~Entity()
+ComponentBase::~ComponentBase()
 {
 }
 
-void Entity::set_interface(std::list<InterfacePort*>*ports)
+void ComponentBase::set_interface(std::list<InterfacePort*>*ports)
 {
 	while (ports->size() > 0) {
 	      ports_.push_back(ports->front());
@@ -42,6 +42,15 @@ void Entity::set_interface(std::list<InterfacePort*>*ports)
 	}
 }
 
+Entity::Entity(perm_string name)
+: ComponentBase(name)
+{
+}
+
+Entity::~Entity()
+{
+}
+
 Architecture* Entity::add_architecture(Architecture*that)
 {
       if (Architecture*tmp = arch_ [that->get_name()]) {

vhdlpp/entity.h

@@ -40,11 +40,17 @@ class InterfacePort : public LineInfo {
       const VType*type;
 };
 
-class Entity : public LineInfo {
+/*
+ * The ComponentBase class represents the base entity
+ * declaration. When used as is, then this represents a forward
+ * declaration of an entity. Elaboration will match it to a proper
+ * entity. Or this can be the base class for a full-out Entity.
+ */
+class ComponentBase : public LineInfo {
 
     public:
-      Entity(perm_string name);
+      ComponentBase(perm_string name);
-      ~Entity();
+      ~ComponentBase();
 
 	// Entities have names.
       perm_string get_name() const { return name_; }
@@ -55,6 +61,27 @@ class Entity : public LineInfo {
 	// empties the list in the process.
       void set_interface(std::list<InterfacePort*>*ports);
 
+    public:
+      void dump_ports(ostream&out) const;
+
+    protected:
+	// This is really only used by the Entity derived class.
+      const std::vector<InterfacePort*>&get_ports() { return ports_; }
+
+    private:
+      perm_string name_;
+      std::vector<InterfacePort*> ports_;
+};
+
+/*
+ * Entities are fully declared components.
+ */
+class Entity : public ComponentBase {
+
+    public:
+      Entity(perm_string name);
+      ~Entity();
+
 	// bind an architecture to the entity, and return the
 	// Architecture that was bound. If there was a previous
 	// architecture with the same name bound, then do not replace
@@ -69,10 +96,6 @@ class Entity : public LineInfo {
       void dump(ostream&out) const;
 
     private:
-      perm_string name_;
-
-      std::vector<InterfacePort*> ports_;
-
       std::map<perm_string,Architecture*>arch_;
       Architecture*bind_arch_;
 

vhdlpp/entity_elaborate.cc

@@ -47,11 +47,11 @@ int Entity::elaborate()
       int errors = 0;
 
       if (verbose_flag)
-	    cerr << "Elaborate entity " << name_ << "..." << endl;
+	    cerr << "Elaborate entity " << get_name() << "..." << endl;
 
       if (arch_.size() == 0) {
 	    cerr << get_fileline() << ": error: "
-		 << "No architectures to choose from for entity " << name_
+		 << "No architectures to choose from for entity " << get_name()
 		 << "." << endl;
 	    return 1;
       }
@@ -59,7 +59,7 @@ int Entity::elaborate()
 
       if (arch_.size() > 1) {
 	    cerr << get_fileline() << ": sorry: "
-		 << "Too many architectures for entity " << name_
+		 << "Too many architectures for entity " << get_name()
 		 << ". Architectures are:" << endl;
 	    for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin()
 		       ; cur != arch_.end() ; ++cur) {
@@ -83,9 +83,10 @@ int Entity::elaborate()
 int Entity::elaborate_ports_(void)
 {
       int errors = 0;
+      const std::vector<InterfacePort*>&ports = get_ports();
 
-      for (std::vector<InterfacePort*>::const_iterator cur = ports_.begin()
+      for (std::vector<InterfacePort*>::const_iterator cur = ports.begin()
-		 ; cur != ports_.end() ; ++cur) {
+		 ; cur != ports.end() ; ++cur) {
 
 	    InterfacePort*cur_port = *cur;
 	    decl_t cur_decl;

vhdlpp/entity_emit.cc

@@ -39,14 +39,16 @@ int Entity::emit(ostream&out)
 {
       int errors = 0;
 
-      out << "module " << name_;
+      const std::vector<InterfacePort*>&ports = get_ports();
+
+      out << "module " << get_name();
 
 	// If there are ports, emit them.
-      if (ports_.size() > 0) {
+      if (ports.size() > 0) {
 	    out << "(";
 	    const char*sep = 0;
-	    for (vector<InterfacePort*>::iterator cur = ports_.begin()
+	    for (vector<InterfacePort*>::const_iterator cur = ports.begin()
-		       ; cur != ports_.end() ; ++cur) {
+		       ; cur != ports.end() ; ++cur) {
 		  InterfacePort*port = *cur;
 
 		  decl_t&decl = declarations_[port->name];

vhdlpp/main.cc

@@ -93,6 +93,7 @@ int main(int argc, char*argv[])
       }
 
       preload_global_types();
+      int errors = 0;
 
       for (int idx = optind ; idx < argc ; idx += 1) {
 	    parse_errors = 0;
@@ -110,20 +111,26 @@ int main(int argc, char*argv[])
 
 	    if (parse_errors > 0) {
 		  fprintf(stderr, "Encountered %d errors parsing %s\n", parse_errors, argv[idx]);
-		  return 2;
 	    }
 	    if (parse_sorrys > 0) {
 		  fprintf(stderr, "Encountered %d unsupported constructs parsing %s\n", parse_sorrys, argv[idx]);
-		  return 2;
 	    }
 
 	    fclose(fd);
+
+	    if (parse_errors || parse_sorrys) {
+		  errors += parse_errors;
+		  errors += parse_sorrys;
+		  break;
+	    }
       }
 
       if (dump_design_entities_path)
 	    dump_design_entities(dump_design_entities_path);
 
-      int errors = 0;
+      if (errors > 0)
+	    return 2;
+
       errors = elaborate_entities();
       if (errors > 0) {
 	    fprintf(stderr, "%d errors elaborating design.\n", errors);

vhdlpp/parse.y

@@ -27,9 +27,11 @@
 # include "parse_misc.h"
 # include "architec.h"
 # include "expression.h"
+# include "vsignal.h"
 # include "vtype.h"
 # include  <cstdarg>
 # include  <list>
+# include  <map>
 
 inline void FILE_NAME(LineInfo*tmp, const struct yyltype&where)
 {
@@ -53,6 +55,18 @@ static void yyerror(const char*msg);
 
 int parse_errors = 0;
 int parse_sorrys = 0;
+
+/*
+ * This map accumulates signals that are matched in the declarations
+ * section of a block. When the declarations are over, these are
+ * transferred to a map for the block proper.
+ */
+static map<perm_string, Signal*> block_signals;
+
+/*
+ * This map accumulates component declarations.
+ */
+static map<perm_string, ComponentBase*> block_components;
 %}
 
 
@@ -145,7 +159,9 @@ architecture_body
     K_of IDENTIFIER
     K_is block_declarative_items_opt
     K_begin architecture_statement_part K_end K_architecture_opt identifier_opt ';'
-      { Architecture*tmp = new Architecture(lex_strings.make($2), *$8);
+      { Architecture*tmp = new Architecture(lex_strings.make($2),
+					    block_signals,
+					    block_components, *$8);
 	FILE_NAME(tmp, @1);
 	bind_architecture_to_entity($4, tmp);
 	if ($11 && tmp->get_name() != $11)
@@ -153,6 +169,8 @@ architecture_body
 	delete[]$2;
 	delete[]$4;
 	delete $8;
+	block_signals.clear();
+	block_components.clear();
 	if ($11) delete[]$11;
       }
   | K_architecture IDENTIFIER
@@ -198,7 +216,15 @@ association_list
 
 block_declarative_item
   : K_signal identifier_list ':' subtype_indication ';'
-      { sorrymsg(@1, "Signal declarations are not supported.\n"); }
+      { /* Save the signal declaration in the block_signals map. */
+	for (std::list<perm_string>::iterator cur = $2->begin()
+		   ; cur != $2->end() ; ++cur) {
+	      Signal*sig = new Signal(*cur, $4);
+	      FILE_NAME(sig, @1);
+	      block_signals[*cur] = sig;
+	}
+	delete $2;
+      }
 
   | K_component IDENTIFIER K_is_opt
     port_clause_opt
@@ -209,10 +235,11 @@ block_declarative_item
 		       $7, name.str());
 	}
 
+	ComponentBase*comp = new ComponentBase(name);
+	if ($4) comp->set_interface($4);
+	block_components[name] = comp;
 	delete[]$2;
-	if ($4) delete $4;
 	delete[]$7;
-	sorrymsg(@1, "Component declarations not supported.\n");
       }
 
       /* Various error handling rules for block_declarative_item... */

vhdlpp/vsignal.cc

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+# include  "vsignal.h"
+
+Signal::Signal(perm_string nam, const VType*typ)
+: name_(nam), type_(typ)
+{
+}
+
+Signal::~Signal()
+{
+}

vhdlpp/vsignal.h

@@ -0,0 +1,44 @@
+#ifndef __vsignal_H
+#define __vsignal_H
+/*
+ * Copyright (c) 2011 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+# include  "StringHeap.h"
+# include  "LineInfo.h"
+
+class VType;
+
+class Signal : public LineInfo {
+
+    public:
+      Signal(perm_string name, const VType*type);
+      ~Signal();
+
+      void dump(ostream&out) const;
+
+    private:
+      perm_string name_;
+      const VType*type_;
+
+    private: // Not implemented
+      Signal(const Signal&);
+      Signal& operator = (const Signal&);
+};
+
+#endif