118 lines
3.0 KiB
C++
118 lines
3.0 KiB
C++
/*
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* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "entity.h"
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# include "architec.h"
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# include <iostream>
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# include <fstream>
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# include <iomanip>
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int emit_entities(void)
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{
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int errors = 0;
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for (map<perm_string,Entity*>::iterator cur = design_entities.begin()
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; cur != design_entities.end() ; ++cur) {
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errors += cur->second->emit(cout);
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}
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return errors;
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}
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int Entity::emit(ostream&out)
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{
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int errors = 0;
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const std::vector<InterfacePort*>&ports = get_ports();
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out << "module " << get_name();
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// If there are ports, emit them.
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if (ports.size() > 0) {
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out << "(";
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const char*sep = 0;
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for (vector<InterfacePort*>::const_iterator cur = ports.begin()
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; cur != ports.end() ; ++cur) {
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InterfacePort*port = *cur;
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decl_t&decl = declarations_[port->name];
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if (sep) out << sep;
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else sep = ", ";
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switch (port->mode) {
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case PORT_NONE: // Should not happen
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out << "NO_PORT " << port->name;
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break;
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case PORT_IN:
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out << "input ";
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if (decl.msb != decl.lsb)
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out << "[" << decl.msb
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<< ":" << decl.lsb << "] ";
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out << port->name;
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break;
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case PORT_OUT:
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out << "output ";
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if (decl.msb != decl.lsb)
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out << "[" << decl.msb
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<< ":" << decl.lsb << "] ";
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out << port->name;
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break;
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}
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}
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cout << ")";
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}
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out << ";" << endl;
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for (map<perm_string,decl_t>::const_iterator cur = declarations_.begin()
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; cur != declarations_.end() ; ++cur) {
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switch (cur->second.type) {
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case VNONE:
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out << "// N type for " << cur->first << endl;
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break;
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case VLOGIC:
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out << "wire logic ";
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if (cur->second.signed_flag)
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out << "signed ";
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if (cur->second.msb != cur->second.lsb)
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out << "[" << cur->second.msb
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<< ":" << cur->second.lsb << "] ";
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out << cur->first << ";" << endl;
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break;
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case VBOOL:
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out << "wire bool ";
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if (cur->second.signed_flag)
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out << "signed ";
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if (cur->second.msb != cur->second.lsb)
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out << "[" << cur->second.msb
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<< ":" << cur->second.lsb << "] ";
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out << cur->first << ";" << endl;
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break;
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}
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}
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errors += bind_arch_->emit(out, this);
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out << "endmodule" << endl;
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return errors;
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}
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