Add regression tests for omitting `parameter` in parameter port list

SystemVerilog allows to completely omit the `parameter` or `localparam`
keyword in the parameter list. Both at the beginning and before redefining
the parameter data type. This is not support in Verilog.

Add regression tests that check that this is supported when in
SystemVerilog mode.

It is not valid to use an implicit data type e.g. just `signed` when
`parameter` was omitted, add regression tests to check for this as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/localparam_implicit3.v

@@ -0,0 +1,30 @@
+// Check that all parameters in a parameter port list after a `localparam` get
+// elaborated as localparams, until the next `parameter`. Check that this is the
+// case even when the data type of the parameter is redefined.
+
+module a #(
+  parameter A = 1, B = 2,
+  localparam C = 3, real D = 4,
+  parameter E = 5
+);
+
+initial begin
+  if (A == 10 && B == 20 && C == 3 && D == 4 && E == 50) begin
+    $display("PASSED");
+  end else begin
+    $display("FAILED");
+  end
+end
+
+endmodule
+
+module b;
+
+  a #(
+    .A(10),
+    .B(20),
+    .D(40), // This will cause an error
+    .E(50)
+  ) i_a();
+
+endmodule

ivtest/ivltests/parameter_omit1.v

@@ -0,0 +1,17 @@
+// Tests that it possible to omit the initial `parameter` keyword in a parameter
+// port list in SystemVerilog. In Verilog this is not allowed and should result
+// in an error.
+
+module a #(A = 1);
+  initial begin
+    if (A == 10) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+endmodule
+
+module test;
+  a #(.A(10)) i_a();
+endmodule

ivtest/ivltests/parameter_omit2.v

@@ -0,0 +1,17 @@
+// Tests that it possible to omit the initial `parameter` keyword in a parameter
+// port list in SystemVerilog. In Verilog this is not allowed and should result
+// in an error.
+
+module a #(integer A = 1);
+  initial begin
+    if (A == 10) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+endmodule
+
+module test;
+  a #(.A(10.1)) i_a();
+endmodule

ivtest/ivltests/parameter_omit3.v

@@ -0,0 +1,17 @@
+// Tests that it possible to omit the `parameter` keyword in a parameter port
+// list before changing the parameter type in SystemVerilog. In Verilog this is
+// not allowed and should result in an error.
+
+module a #(parameter real A = 1.0, integer B = 2);
+  initial begin
+    if (A == 10.1 && B == 20) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+endmodule
+
+module test;
+  a #(.A(10.1), .B(20)) i_a();
+endmodule

ivtest/ivltests/parameter_omit_invalid1.v

@@ -0,0 +1,8 @@
+// Check that implicit type in a parameter port list without `parameter`
+// generates an error.
+
+module test #([7:0] A = 1);
+  initial begin
+    $display("FAILED");
+  end
+endmodule

ivtest/ivltests/parameter_omit_invalid2.v

@@ -0,0 +1,8 @@
+// Check that implicit type in a parameter port list without `parameter`
+// generates an error.
+
+module test #(signed A = 1);
+  initial begin
+    $display("FAILED");
+  end
+endmodule

ivtest/ivltests/parameter_omit_invalid3.v

@@ -0,0 +1,8 @@
+// Check that declaring changing the parameter type to an implicit type without
+// the `parameter` keyword results in an error.
+
+module test #(parameter real A = 1.0, signed B = 2);
+  initial begin
+    $display("FAILED");
+  end
+endmodule

ivtest/regress-fsv.list

@@ -78,6 +78,9 @@ br_gh567		normal			ivltests
 check_constant_3	normal			ivltests
 function4		normal			ivltests
 parameter_in_generate1	normal			ivltests
+parameter_omit1		normal			ivltests
+parameter_omit2		normal			ivltests
+parameter_omit3		normal			ivltests
 pr1963962		normal			ivltests gold=pr1963962-fsv.gold
 pr3015421		CE			ivltests gold=pr3015421-fsv.gold
 resetall		normal,-Wtimescale	ivltests gold=resetall-fsv.gold

ivtest/regress-sv.list

@@ -302,6 +302,7 @@ l_equiv_const		normal,-g2005-sv	ivltests
 line_directive		normal,-g2009,-I./ivltests	ivltests gold=line_directive.gold
 localparam_implicit	normal,-g2005-sv	ivltests
 localparam_implicit2	CE,-g2005-sv	ivltests
+localparam_implicit3	CE,-g2005-sv	ivltests
 localparam_query	normal,-g2005-sv	ivltests
 localparam_type2	normal,-g2009		ivltests
 logical_short_circuit	normal,-g2012		ivltests

ivtest/regress-vlg.list

@@ -695,6 +695,12 @@ param_test4		normal			ivltests
 param_times		normal			ivltests # param has multiplication.
 parameter_type		normal			ivltests gold=parameter_type.gold
 parameter_in_generate1	CE			ivltests
+parameter_omit1		CE			ivltests
+parameter_omit2		CE			ivltests
+parameter_omit3		CE			ivltests
+parameter_omit_invalid1	CE			ivltests
+parameter_omit_invalid2	CE			ivltests
+parameter_omit_invalid3	CE			ivltests
 patch1268		normal			ivltests
 pca1			normal			ivltests # Procedural Continuous Assignment in a mux
 pic			normal			contrib  pictest gold=pic.gold