From 79fc09717ed45c95936935a580dc961452b91c19 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 19 Jun 2023 07:51:13 -0700 Subject: [PATCH] Add regression test for module array port initializers Check that initializers are supported for module array ports. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_port_array_init1.v | 23 +++++++++++++++++++ ivtest/regress-vvp.list | 1 + ivtest/vvp_tests/module_port_array_init1.json | 5 ++++ 3 files changed, 29 insertions(+) create mode 100644 ivtest/ivltests/module_port_array_init1.v create mode 100644 ivtest/vvp_tests/module_port_array_init1.json diff --git a/ivtest/ivltests/module_port_array_init1.v b/ivtest/ivltests/module_port_array_init1.v new file mode 100644 index 000000000..f08462927 --- /dev/null +++ b/ivtest/ivltests/module_port_array_init1.v @@ -0,0 +1,23 @@ +// Check that initializers values are supported for module array ports + +module M ( + input [31:0] x[0:1] = '{1, 2}, + output reg [31:0] y[0:1] = '{3, 4} +); + + initial begin + #1 + if (x[0] === 1 && x[1] === 2 && y[0] === 3 && y[1] === 4) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule + +module test; + + M i_m (); + +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index 41501aaa6..8ab931c1a 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -35,6 +35,7 @@ memsynth1 vvp_tests/memsynth1.json module_ordered_list1 vvp_tests/module_ordered_list1.json module_ordered_list2 vvp_tests/module_ordered_list2.json module_port_array1 vvp_tests/module_port_array1.json +module_port_array_init1 vvp_tests/module_port_array_init1.json param-width vvp_tests/param-width.json param-width-vlog95 vvp_tests/param-width-vlog95.json pr1388974 vvp_tests/pr1388974.json diff --git a/ivtest/vvp_tests/module_port_array_init1.json b/ivtest/vvp_tests/module_port_array_init1.json new file mode 100644 index 000000000..ec34b89b7 --- /dev/null +++ b/ivtest/vvp_tests/module_port_array_init1.json @@ -0,0 +1,5 @@ +{ + "type" : "normal", + "source" : "module_port_array_init1.v", + "iverilog-args" : [ "-g2005-sv" ] +}