diff --git a/vhdlpp/Makefile.in b/vhdlpp/Makefile.in index c5abc4d69..2f643433e 100644 --- a/vhdlpp/Makefile.in +++ b/vhdlpp/Makefile.in @@ -60,7 +60,9 @@ LIBS = @LIBS@ @EXTRALIBS@ M = StringHeap.o LineInfo.o O = main.o architec.o compiler.o entity.o entity_elaborate.o \ - expression.o lexor.o lexor_keyword.o parse.o vhdlreal.o vhdlint.o debug.o $M + expression.o lexor.o lexor_keyword.o parse.o vhdlreal.o vhdlint.o debug.o \ + architec_emit.o entity_emit.o expression_emit.o \ + $M all: dep vhdlpp@EXEEXT@ diff --git a/vhdlpp/architec.h b/vhdlpp/architec.h index 90659d04f..62fc0694e 100644 --- a/vhdlpp/architec.h +++ b/vhdlpp/architec.h @@ -23,6 +23,7 @@ # include "LineInfo.h" # include +class Entity; class Expression; /* @@ -41,6 +42,7 @@ class Architecture : public LineInfo { Statement(); virtual ~Statement() =0; + virtual int emit(ostream&out, Entity*ent, Architecture*arc); virtual void dump(ostream&out) const; private: @@ -56,6 +58,13 @@ class Architecture : public LineInfo { perm_string get_name() const { return name_; } + // Emit this architecture to the given out file in the context + // of the specified entity. This method is used by the + // elaborate code to display generated code to the specified + // output. + int emit(ostream&out, Entity*entity); + + // The dump method writes a debug display to the given output. void dump(ostream&out, perm_string of_entity) const; private: @@ -76,6 +85,7 @@ class SignalAssignment : public Architecture::Statement { SignalAssignment(perm_string target_name, std::list&rval); ~SignalAssignment(); + int emit(ostream&out, Entity*entity, Architecture*arc); virtual void dump(ostream&out) const; private: diff --git a/vhdlpp/architec_emit.cc b/vhdlpp/architec_emit.cc new file mode 100644 index 000000000..d71f45386 --- /dev/null +++ b/vhdlpp/architec_emit.cc @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2011 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include "architec.h" +# include "entity.h" +# include "expression.h" +# include +# include +# include + +int Architecture::emit(ostream&out, Entity*entity) +{ + int errors = 0; + for (list::iterator cur = statements_.begin() + ; cur != statements_.end() ; ++cur) { + + errors += (*cur)->emit(out, entity, this); + } + + return errors; +} + +int Architecture::Statement::emit(ostream&out, Entity*, Architecture*) +{ + out << " // " << get_fileline() << ": internal error: " + << "I don't know how to emit this statement! " + << "type=" << typeid(*this).name() << endl; + return 1; +} + +int SignalAssignment::emit(ostream&out, Entity*ent, Architecture*arc) +{ + int errors = 0; + + assert(rval_.size() == 1); + Expression*rval = rval_.front(); + + out << "// " << get_fileline() << endl; + out << "assign " << target_name_ << " = "; + + errors += rval->emit(out, ent, arc); + + out << ";" << endl; + return errors; +} + diff --git a/vhdlpp/entity.h b/vhdlpp/entity.h index 5ab750fd5..2974a6fb4 100644 --- a/vhdlpp/entity.h +++ b/vhdlpp/entity.h @@ -56,6 +56,7 @@ class Entity : public LineInfo { Architecture* add_architecture(Architecture*); int elaborate(); + int emit(ostream&out); void dump(ostream&out) const; @@ -66,6 +67,8 @@ class Entity : public LineInfo { perm_string name_; std::maparch_; + + Architecture*bind_arch_; }; /* @@ -80,6 +83,8 @@ extern std::map design_entities; */ extern int elaborate_entities(void); +extern int emit_entities(void); + /* * Use this function to dump a description of the design entities to a * file. This is for debug, not for any useful purpose. diff --git a/vhdlpp/entity_elaborate.cc b/vhdlpp/entity_elaborate.cc index 6a860ffc5..95977a6b6 100644 --- a/vhdlpp/entity_elaborate.cc +++ b/vhdlpp/entity_elaborate.cc @@ -19,6 +19,7 @@ # include "entity.h" # include "compiler.h" +# include "architec.h" # include # include # include @@ -44,47 +45,32 @@ int Entity::elaborate() if (verbose_flag) cerr << "Elaborate entity " << name_ << "..." << endl; - cout << "module " << name_; - - // If there are ports, emit them. - if (ports.size() > 0) { - cout << "("; - const char*sep = 0; - for (vector::iterator cur = ports.begin() - ; cur != ports.end() ; ++cur) { - InterfacePort*port = *cur; - - // FIXME: this is a stub. This port handling code - // currently only supports std_logic signal tyes, - // so just assert that the user asked for std_logic. - if (port->type_name != "std_logic") { - cerr << "sorry: VHDL only supports std_logic ports." - << " Expecting std_logic, but got \"" - << port->type_name << "\"" << endl; - errors += 1; - } - - if (sep) cout << sep; - else sep = ", "; - - switch (port->mode) { - case PORT_NONE: // Should not happen - cout << "NO_PORT " << port->name; - break; - case PORT_IN: - cout << "input " << port->name; - break; - case PORT_OUT: - cout << "output " << port->name; - break; - } - } - cout << ")"; + if (arch_.size() == 0) { + cerr << get_fileline() << ": error: " + << "No architectures to choose from for entity " << name_ + << "." << endl; + return 1; } - cout << ";" << endl; - cout << "endmodule" << endl; + if (arch_.size() > 1) { + cerr << get_fileline() << ": sorry: " + << "Too many architectures for entity " << name_ + << ". Architectures are:" << endl; + for (map::const_iterator cur = arch_.begin() + ; cur != arch_.end() ; ++cur) { + cerr << get_fileline() << ": : " << cur->first + << " at " << cur->second->get_fileline() << endl; + } + + errors += 1; + } + + bind_arch_ = arch_.begin()->second; + if (verbose_flag) + cerr << "For entity " << get_name() + << ", choosing architecture " << bind_arch_->get_name() + << "." << endl; return errors; } diff --git a/vhdlpp/entity_emit.cc b/vhdlpp/entity_emit.cc new file mode 100644 index 000000000..03299e83e --- /dev/null +++ b/vhdlpp/entity_emit.cc @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2011 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include "entity.h" +# include "architec.h" +# include +# include +# include + +int emit_entities(void) +{ + int errors = 0; + + for (map::iterator cur = design_entities.begin() + ; cur != design_entities.end() ; ++cur) { + errors += cur->second->emit(cout); + } + + return errors; +} + +int Entity::emit(ostream&out) +{ + int errors = 0; + + out << "module " << name_; + + // If there are ports, emit them. + if (ports.size() > 0) { + out << "("; + const char*sep = 0; + for (vector::iterator cur = ports.begin() + ; cur != ports.end() ; ++cur) { + InterfacePort*port = *cur; + + // FIXME: this is a stub. This port handling code + // currently only supports std_logic signal tyes, + // so just assert that the user asked for std_logic. + if (port->type_name != "std_logic") { + cerr << "sorry: VHDL only supports std_logic ports." + << " Expecting std_logic, but got \"" + << port->type_name << "\"" << endl; + errors += 1; + } + + if (sep) out << sep; + else sep = ", "; + + switch (port->mode) { + case PORT_NONE: // Should not happen + out << "NO_PORT " << port->name; + break; + case PORT_IN: + out << "input " << port->name; + break; + case PORT_OUT: + out << "output " << port->name; + break; + } + } + cout << ")"; + } + + out << ";" << endl; + + errors += bind_arch_->emit(out, this); + + out << "endmodule" << endl; + + return errors; +} diff --git a/vhdlpp/expression.h b/vhdlpp/expression.h index 8ef663826..dae333c5c 100644 --- a/vhdlpp/expression.h +++ b/vhdlpp/expression.h @@ -22,6 +22,9 @@ # include "StringHeap.h" # include "LineInfo.h" +class Entity; +class Architecture; + /* * The Expression class represents parsed expressions from the parsed * VHDL input. The Expression class is a virtual class that holds more @@ -33,6 +36,12 @@ class Expression : public LineInfo { Expression(); virtual ~Expression() =0; + // The emit virtual method is called bu architecture emit to + // output the generated code for the expression. The derived + // class fills in the details of what exactly happend. + virtual int emit(ostream&out, Entity*ent, Architecture*arc); + + // Debug dump of the expression. virtual void dump(ostream&out, int indent) const; private: @@ -51,6 +60,7 @@ class ExpLogical : public Expression { ExpLogical(ExpLogical::fun_t ty, Expression*op1, Expression*op2); ~ExpLogical(); + int emit(ostream&out, Entity*ent, Architecture*arc); void dump(ostream&out, int indent) const; private: @@ -69,6 +79,7 @@ class ExpName : public Expression { ExpName(perm_string nn); ~ExpName(); + int emit(ostream&out, Entity*ent, Architecture*arc); void dump(ostream&out, int indent) const; private: diff --git a/vhdlpp/expression_emit.cc b/vhdlpp/expression_emit.cc new file mode 100644 index 000000000..97280ccf7 --- /dev/null +++ b/vhdlpp/expression_emit.cc @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2011 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include "expression.h" +# include +# include + +using namespace std; + +int Expression::emit(ostream&out, Entity*, Architecture*) +{ + out << " /* " << get_fileline() << ": internal error: " + << "I don't know how to emit this expression! " + << "type=" << typeid(*this).name() << " */ "; + return 1; +} + +int ExpLogical::emit(ostream&out, Entity*ent, Architecture*arc) +{ + int errors = 0; + + errors += operand1_->emit(out, ent, arc); + + switch (fun_) { + case AND: + out << " & "; + break; + case OR: + out << " | "; + break; + case XOR: + out << " ^ "; + break; + case NAND: + out << " ~& "; + break; + case NOR: + out << " ~| "; + break; + case XNOR: + out << " ~^ "; + break; + } + + errors += operand2_->emit(out, ent, arc); + + return errors; +} + +int ExpName::emit(ostream&out, Entity*, Architecture*) +{ + int errors = 0; + + out << name_; + return errors; +} diff --git a/vhdlpp/main.cc b/vhdlpp/main.cc index 598187952..dc7f12b82 100644 --- a/vhdlpp/main.cc +++ b/vhdlpp/main.cc @@ -115,13 +115,19 @@ int main(int argc, char*argv[]) if (dump_design_entities_path) dump_design_entities(dump_design_entities_path); - int elaborate_errors = 0; - elaborate_errors = elaborate_entities(); - if (elaborate_errors > 0) { - fprintf(stderr, "%d errors elaborating design.\n", elaborate_errors); + int errors = 0; + errors = elaborate_entities(); + if (errors > 0) { + fprintf(stderr, "%d errors elaborating design.\n", errors); return 3; } + errors = emit_entities(); + if (errors > 0) { + fprintf(stderr, "%d errors emitting design.\n", errors); + return 4; + } + lex_strings.cleanup(); return 0; }