diff --git a/tgt-fpga/d-generic-edif.c b/tgt-fpga/d-generic-edif.c index 9b25c63aa..ea7a5e0bb 100644 --- a/tgt-fpga/d-generic-edif.c +++ b/tgt-fpga/d-generic-edif.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: d-generic-edif.c,v 1.14 2003/06/17 03:47:41 steve Exp $" +#ident "$Id: d-generic-edif.c,v 1.15 2003/06/24 03:55:00 steve Exp $" #endif # include "device.h" @@ -459,6 +459,7 @@ void edif_show_generic_dff(ivl_lpm_t net) const struct device_s d_generic_edif = { edif_show_header, edif_show_footer, + 0, /* show_cell_scope not implemented. */ 0, /* draw_pad not implemented */ edif_show_logic, edif_show_generic_dff, @@ -475,6 +476,9 @@ const struct device_s d_generic_edif = { /* * $Log: d-generic-edif.c,v $ + * Revision 1.15 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.14 2003/06/17 03:47:41 steve * Handle bufz as buf in generic fpga/edif target. * diff --git a/tgt-fpga/d-generic.c b/tgt-fpga/d-generic.c index ee80334a5..738fe3641 100644 --- a/tgt-fpga/d-generic.c +++ b/tgt-fpga/d-generic.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: d-generic.c,v 1.12 2002/10/28 02:05:56 steve Exp $" +#ident "$Id: d-generic.c,v 1.13 2003/06/24 03:55:00 steve Exp $" #endif # include "device.h" @@ -498,6 +498,7 @@ static void generic_show_add(ivl_lpm_t net) const struct device_s d_generic = { generic_show_header, generic_show_footer, + 0, /* show_scope */ 0, /* show_pad not implemented */ generic_show_logic, generic_show_dff, @@ -514,6 +515,9 @@ const struct device_s d_generic = { /* * $Log: d-generic.c,v $ + * Revision 1.13 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.12 2002/10/28 02:05:56 steve * Add Virtex code generators for left shift, * subtraction, and GE comparators. diff --git a/tgt-fpga/d-virtex.c b/tgt-fpga/d-virtex.c index eb9c45b7b..9d1bda3ed 100644 --- a/tgt-fpga/d-virtex.c +++ b/tgt-fpga/d-virtex.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: d-virtex.c,v 1.22 2003/02/26 01:24:42 steve Exp $" +#ident "$Id: d-virtex.c,v 1.23 2003/06/24 03:55:00 steve Exp $" #endif # include "device.h" @@ -1924,6 +1924,7 @@ static void virtex_show_shiftl(ivl_lpm_t net) const struct device_s d_virtex_edif = { edif_show_header, edif_show_footer, + 0, /* show_scope not implemented */ edif_show_virtex_pad, edif_show_virtex_logic, edif_show_generic_dff, @@ -1940,6 +1941,9 @@ const struct device_s d_virtex_edif = { /* * $Log: d-virtex.c,v $ + * Revision 1.23 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.22 2003/02/26 01:24:42 steve * ivl_lpm_name is obsolete. * diff --git a/tgt-fpga/d-virtex2.c b/tgt-fpga/d-virtex2.c index c86c50cd0..2aa66d58b 100644 --- a/tgt-fpga/d-virtex2.c +++ b/tgt-fpga/d-virtex2.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: d-virtex2.c,v 1.10 2003/04/05 05:53:34 steve Exp $" +#ident "$Id: d-virtex2.c,v 1.11 2003/06/24 03:55:00 steve Exp $" #endif # include "device.h" @@ -49,7 +49,10 @@ static edif_cell_t cell_1 = 0; static edif_cell_t cell_ipad = 0; static edif_cell_t cell_opad = 0; - +/* + * This is a table of cell types that are accessible via the cellref + * attribute to a gate. + */ const static struct edif_xlib_celltable virtex2_celltable[] = { { "BUFG", xilinx_cell_bufg }, { "MULT_AND", xilinx_cell_mult_and }, @@ -177,6 +180,33 @@ static void virtex2_show_footer(ivl_design_t des) edif_print(xnf, edf); } +/* + * Make (or retreive) a cell in the external library that reflects the + * scope with its ports. + */ +static void virtex2_show_scope(ivl_scope_t scope) +{ + edif_cell_t cell; + edif_cellref_t ref; + + unsigned port, idx; + + cell = edif_xlibrary_scope_cell(xlib, scope); + ref = edif_cellref_create(edf, cell); + + for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) { + edif_joint_t jnt; + ivl_signal_t sig = ivl_scope_sig(scope, idx); + + if (ivl_signal_port(sig) == IVL_SIP_NONE) + continue; + + port = edif_cell_port_byname(cell, ivl_signal_basename(sig)); + jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0)); + edif_add_to_joint(jnt, ref, port); + } +} + static void virtex2_pad(ivl_signal_t sig, const char*str) { unsigned idx; @@ -1080,6 +1110,7 @@ static void virtex2_cmp_ge(ivl_lpm_t net) const struct device_s d_virtex2_edif = { virtex2_show_header, virtex2_show_footer, + virtex2_show_scope, virtex2_pad, virtex2_logic, virtex2_generic_dff, @@ -1096,6 +1127,9 @@ const struct device_s d_virtex2_edif = { /* * $Log: d-virtex2.c,v $ + * Revision 1.11 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.10 2003/04/05 05:53:34 steve * Move library cell management to common file. * diff --git a/tgt-fpga/device.h b/tgt-fpga/device.h index af36170cf..d2afccc65 100644 --- a/tgt-fpga/device.h +++ b/tgt-fpga/device.h @@ -1,7 +1,7 @@ #ifndef __device_H #define __device_H /* - * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: device.h,v 1.10 2002/10/28 02:05:56 steve Exp $" +#ident "$Id: device.h,v 1.11 2003/06/24 03:55:00 steve Exp $" #endif # include @@ -41,6 +41,8 @@ struct device_s { /* These methods draw leading and trailing format text. */ void (*show_header)(ivl_design_t des); void (*show_footer)(ivl_design_t des); + /* Draw scopes marked by ivl_synthesis_cell */ + void (*show_cell_scope)(ivl_scope_t net); /* Draw pads connected to the specified signal. */ void (*show_pad)(ivl_signal_t sig, const char*str); /* Draw basic logic devices. */ @@ -73,6 +75,9 @@ extern device_t device_from_arch(const char*arch); /* * $Log: device.h,v $ + * Revision 1.11 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.10 2002/10/28 02:05:56 steve * Add Virtex code generators for left shift, * subtraction, and GE comparators. diff --git a/tgt-fpga/edif.c b/tgt-fpga/edif.c index 76f9c975b..6f45e56e8 100644 --- a/tgt-fpga/edif.c +++ b/tgt-fpga/edif.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: edif.c,v 1.4 2003/04/04 04:59:03 steve Exp $" +#ident "$Id: edif.c,v 1.5 2003/06/24 03:55:00 steve Exp $" #endif # include "edif.h" @@ -199,6 +199,45 @@ edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t xlib, return 0; } +edif_cell_t edif_xlibrary_scope_cell(edif_xlibrary_t xlib, + ivl_scope_t scope) +{ + unsigned port_count, idx; + edif_cell_t cur; + + /* Check to see if the cell is already somehow defined. */ + cur = edif_xlibrary_findcell(xlib, ivl_scope_tname(scope)); + if (cur) return cur; + + /* Count the ports of the scope. */ + port_count = 0; + for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) { + ivl_signal_t sig = ivl_scope_sig(scope, idx); + + if (ivl_signal_port(sig) == IVL_SIP_NONE) + continue; + + port_count += 1; + } + + cur = edif_xcell_create(xlib, ivl_scope_tname(scope), port_count); + + port_count = 0; + for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) { + ivl_signal_t sig = ivl_scope_sig(scope, idx); + + if (ivl_signal_port(sig) == IVL_SIP_NONE) + continue; + + edif_cell_portconfig(cur, port_count, + ivl_signal_basename(sig), + ivl_signal_port(sig)); + port_count += 1; + } + + return cur; +} + edif_cell_t edif_xcell_create(edif_xlibrary_t xlib, const char*name, unsigned nports) { @@ -491,6 +530,9 @@ void edif_print(FILE*fd, edif_t edf) /* * $Log: edif.c,v $ + * Revision 1.5 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.4 2003/04/04 04:59:03 steve * Add xlibrary celltable. * diff --git a/tgt-fpga/edif.h b/tgt-fpga/edif.h index 557f11730..fb7162cde 100644 --- a/tgt-fpga/edif.h +++ b/tgt-fpga/edif.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: edif.h,v 1.3 2003/04/04 04:59:03 steve Exp $" +#ident "$Id: edif.h,v 1.4 2003/06/24 03:55:00 steve Exp $" #endif # include @@ -150,6 +150,11 @@ extern void edif_xlibrary_set_celltable(edif_xlibrary_t lib, extern edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t lib, const char*cell_name); +/* Similar to the above, but it gets the information it needs from the + ivl_scope_t object. */ +extern edif_cell_t edif_xlibrary_scope_cell(edif_xlibrary_t xlib, + ivl_scope_t scope); + /* Create a new cell, attached to the external library. Specify the number of ports that the cell has. The edif_cell_portconfig function is then used to assign name and direction to each of the @@ -211,6 +216,9 @@ extern void edif_print(FILE*fd, edif_t design); /* * $Log: edif.h,v $ + * Revision 1.4 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.3 2003/04/04 04:59:03 steve * Add xlibrary celltable. * diff --git a/tgt-fpga/fpga.c b/tgt-fpga/fpga.c index 952e927c8..d6acde6b6 100644 --- a/tgt-fpga/fpga.c +++ b/tgt-fpga/fpga.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: fpga.c,v 1.6 2002/08/12 01:35:02 steve Exp $" +#ident "$Id: fpga.c,v 1.7 2003/06/24 03:55:00 steve Exp $" #endif # include "config.h" @@ -27,6 +27,7 @@ */ # include +# include # include "fpga_priv.h" @@ -38,8 +39,29 @@ const char*part = 0; const char*arch = 0; device_t device = 0; +int scope_has_attribute(ivl_scope_t s, const char *name) +{ + int i; + const struct ivl_attribute_s *a; + for (i=0; ikey); + if (strcmp(a->key,name) == 0) + return 1; + } + return 0; +} + static int show_process(ivl_process_t net, void*x) { + ivl_scope_t scope = ivl_process_scope(net); + + /* Ignore processes that are within scopes that are cells. The + cell_scope will generate a cell to represent the entire + scope. */ + if (scope_has_attribute(scope, "ivl_synthesis_cell")) + return 0; + fprintf(stderr, "fpga target: unsynthesized behavioral code\n"); return 0; } @@ -123,6 +145,9 @@ int target_design(ivl_design_t des) /* * $Log: fpga.c,v $ + * Revision 1.7 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.6 2002/08/12 01:35:02 steve * conditional ident string using autoconfig. * diff --git a/tgt-fpga/fpga_priv.h b/tgt-fpga/fpga_priv.h index 8226106bb..d7e55da1a 100644 --- a/tgt-fpga/fpga_priv.h +++ b/tgt-fpga/fpga_priv.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: fpga_priv.h,v 1.6 2002/08/12 01:35:03 steve Exp $" +#ident "$Id: fpga_priv.h,v 1.7 2003/06/24 03:55:00 steve Exp $" #endif # include @@ -37,6 +37,11 @@ extern device_t device; extern const char*part; extern const char*arch; +/* + * Attribute lookup, should this be provided in ivl_target.h? + */ +int scope_has_attribute(ivl_scope_t s, const char *name); + /* * These are mangle functions. */ @@ -83,6 +88,9 @@ extern unsigned edif_uref; /* * $Log: fpga_priv.h,v $ + * Revision 1.7 2003/06/24 03:55:00 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.6 2002/08/12 01:35:03 steve * conditional ident string using autoconfig. * diff --git a/tgt-fpga/gates.c b/tgt-fpga/gates.c index 96bfeebad..09352684c 100644 --- a/tgt-fpga/gates.c +++ b/tgt-fpga/gates.c @@ -17,13 +17,24 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: gates.c,v 1.10 2002/10/28 02:05:56 steve Exp $" +#ident "$Id: gates.c,v 1.11 2003/06/24 03:55:01 steve Exp $" #endif # include # include "fpga_priv.h" # include +static void show_cell_scope(ivl_scope_t scope) +{ + if (device->show_cell_scope == 0) { + fprintf(stderr, "fpga.tgt: ivl_synthesis_cell(scope)" + " not supported by this target.\n"); + return; + } + + device->show_cell_scope(scope); +} + static void show_gate_logic(ivl_net_logic_t net) { device->show_logic(net); @@ -125,6 +136,11 @@ int show_scope_gates(ivl_scope_t net, void*x) { unsigned idx; + if (scope_has_attribute(net, "ivl_synthesis_cell")) { + show_cell_scope(net); + return 0; + } + for (idx = 0 ; idx < ivl_scope_logs(net) ; idx += 1) show_gate_logic(ivl_scope_log(net, idx)); @@ -136,6 +152,9 @@ int show_scope_gates(ivl_scope_t net, void*x) /* * $Log: gates.c,v $ + * Revision 1.11 2003/06/24 03:55:01 steve + * Add ivl_synthesis_cell support for virtex2. + * * Revision 1.10 2002/10/28 02:05:56 steve * Add Virtex code generators for left shift, * subtraction, and GE comparators. @@ -156,21 +175,5 @@ int show_scope_gates(ivl_scope_t net, void*x) * so that non-XNF code generation is also possible. * * Start into the virtex EDIF output driver. - * - * Revision 1.5 2001/09/01 04:30:44 steve - * Generic ADD code. - * - * Revision 1.4 2001/09/01 02:28:42 steve - * Generate code for MUX devices. - * - * Revision 1.3 2001/09/01 02:01:30 steve - * identity compare, and PWR records for constants. - * - * Revision 1.2 2001/08/30 04:31:04 steve - * Mangle nexus names. - * - * Revision 1.1 2001/08/28 04:14:20 steve - * Add the fpga target. - * */