Generate MUXF5 based 4-input N-wide muxes.
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steve
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dccd7ec7e2
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7734ba99fc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex.c,v 1.30 2003/07/02 03:02:15 steve Exp $"
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#ident "$Id: d-virtex.c,v 1.31 2003/07/04 00:10:09 steve Exp $"
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#endif
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# include "device.h"
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@ -616,6 +616,77 @@ void virtex_ge(ivl_lpm_t net)
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_O);
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}
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/*
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* A 4-input N-wide mux can be made on Virtex devices using MUXF5 and
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* LUT devices. The MUXF5 selects a LUT device (and is connected to
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* S[1]) and the LUT devices, connected to S[0], select the input.
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*/
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static void virtex_mux4(ivl_lpm_t net)
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{
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unsigned idx;
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assert(ivl_lpm_selects(net) == 2);
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for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
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edif_joint_t jnt;
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edif_cellref_t lut01;
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edif_cellref_t lut23;
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edif_cellref_t muxf5;
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lut01 = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
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edif_cellref_pstring(lut01, "INIT", "CA");
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lut23 = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
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edif_cellref_pstring(lut23, "INIT", "CA");
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muxf5 = edif_cellref_create(edf, xilinx_cell_muxf5(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 0, idx));
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edif_add_to_joint(jnt, lut01, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 1, idx));
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edif_add_to_joint(jnt, lut01, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 2, idx));
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edif_add_to_joint(jnt, lut23, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 3, idx));
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edif_add_to_joint(jnt, lut23, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net, 0));
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edif_add_to_joint(jnt, lut01, LUT_I2);
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edif_add_to_joint(jnt, lut23, LUT_I2);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxf5, MUXF_I0);
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edif_add_to_joint(jnt, lut01, LUT_O);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxf5, MUXF_I1);
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edif_add_to_joint(jnt, lut23, LUT_O);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
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edif_add_to_joint(jnt, muxf5, MUXF_O);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net, 1));
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edif_add_to_joint(jnt, muxf5, MUXF_S);
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}
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}
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void virtex_mux(ivl_lpm_t net)
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{
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switch (ivl_lpm_selects(net)) {
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case 2:
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virtex_mux4(net);
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break;
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default:
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xilinx_mux(net);
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break;
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}
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}
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/*
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* This function generates ADD/SUB devices for Virtex devices,
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* based on the documented implementations of ADD8/ADD16, etc., from
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@ -750,7 +821,7 @@ const struct device_s d_virtex_edif = {
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virtex_eq,
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virtex_eq,
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virtex_ge,
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xilinx_mux,
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virtex_mux,
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virtex_add,
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virtex_add,
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xilinx_shiftl,
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@ -760,6 +831,9 @@ const struct device_s d_virtex_edif = {
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/*
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* $Log: d-virtex.c,v $
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* Revision 1.31 2003/07/04 00:10:09 steve
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* Generate MUXF5 based 4-input N-wide muxes.
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*
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* Revision 1.30 2003/07/02 03:02:15 steve
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* More xilinx common code.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex2.c,v 1.17 2003/07/02 03:02:15 steve Exp $"
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#ident "$Id: d-virtex2.c,v 1.18 2003/07/04 00:10:09 steve Exp $"
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#endif
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# include "device.h"
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@ -84,7 +84,7 @@ const struct device_s d_virtex2_edif = {
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virtex_eq,
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virtex_eq,
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virtex_ge,
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xilinx_mux,
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virtex_mux,
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virtex_add,
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virtex_add,
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xilinx_shiftl, /* show_shiftl */
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@ -94,6 +94,9 @@ const struct device_s d_virtex2_edif = {
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/*
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* $Log: d-virtex2.c,v $
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* Revision 1.18 2003/07/04 00:10:09 steve
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* Generate MUXF5 based 4-input N-wide muxes.
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*
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* Revision 1.17 2003/07/02 03:02:15 steve
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* More xilinx common code.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.c,v 1.7 2003/07/03 17:46:33 steve Exp $"
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#ident "$Id: xilinx.c,v 1.8 2003/07/04 00:10:09 steve Exp $"
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#endif
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# include "edif.h"
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@ -99,6 +99,32 @@ edif_cell_t xilinx_cell_inv(edif_xlibrary_t xlib)
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return cell;
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}
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edif_cell_t xilinx_cell_muxf5(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "MUXF5", 4);
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edif_cell_portconfig(cell, MUXF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, MUXF_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXF_I1, "I1", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXF_S, "S", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_muxf6(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "MUXF6", 4);
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edif_cell_portconfig(cell, MUXF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, MUXF_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXF_I1, "I1", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXF_S, "S", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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@ -899,6 +925,9 @@ void xilinx_shiftl(ivl_lpm_t net)
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/*
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* $Log: xilinx.c,v $
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* Revision 1.8 2003/07/04 00:10:09 steve
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* Generate MUXF5 based 4-input N-wide muxes.
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*
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* Revision 1.7 2003/07/03 17:46:33 steve
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* IOPAD support.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.h,v 1.6 2003/07/02 03:02:15 steve Exp $"
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#ident "$Id: xilinx.h,v 1.7 2003/07/04 00:10:09 steve Exp $"
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#endif
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/*
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@ -96,12 +96,23 @@ extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
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#define XORCY_CI 1
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#define XORCY_LI 2
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/* === Virtex/Virtex2 MUX devices */
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extern edif_cell_t xilinx_cell_muxf5(edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_muxf6(edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_muxf7(edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_muxf8(edif_xlibrary_t xlib);
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#define MUXF_O 0
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#define MUXF_I0 1
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#define MUXF_I1 2
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#define MUXF_S 3
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/* === Inheritable Methods === */
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extern void virtex_logic(ivl_net_logic_t net);
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extern void virtex_generic_dff(ivl_lpm_t net);
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extern void virtex_eq(ivl_lpm_t net);
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extern void virtex_ge(ivl_lpm_t net);
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extern void virtex_mux(ivl_lpm_t net);
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extern void virtex_add(ivl_lpm_t net);
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extern void xilinx_common_header(ivl_design_t des);
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@ -115,6 +126,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
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/*
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* $Log: xilinx.h,v $
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* Revision 1.7 2003/07/04 00:10:09 steve
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* Generate MUXF5 based 4-input N-wide muxes.
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*
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* Revision 1.6 2003/07/02 03:02:15 steve
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* More xilinx common code.
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*
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