diff --git a/tgt-fpga/d-virtex.c b/tgt-fpga/d-virtex.c
index 7b4fc9564..7889824a1 100644
--- a/tgt-fpga/d-virtex.c
+++ b/tgt-fpga/d-virtex.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: d-virtex.c,v 1.30 2003/07/02 03:02:15 steve Exp $"
+#ident "$Id: d-virtex.c,v 1.31 2003/07/04 00:10:09 steve Exp $"
 #endif
 
 # include  "device.h"
@@ -616,6 +616,77 @@ void virtex_ge(ivl_lpm_t net)
       edif_add_to_joint(jnt, muxcy_prev, MUXCY_O);
 }
 
+/*
+ * A 4-input N-wide mux can be made on Virtex devices using MUXF5 and
+ * LUT devices. The MUXF5 selects a LUT device (and is connected to
+ * S[1]) and the LUT devices, connected to S[0], select the input.
+ */
+static void virtex_mux4(ivl_lpm_t net)
+{
+      unsigned idx;
+      assert(ivl_lpm_selects(net) == 2);
+
+      for (idx = 0 ;  idx < ivl_lpm_width(net) ;  idx += 1) {
+	    edif_joint_t jnt;
+	    edif_cellref_t lut01;
+	    edif_cellref_t lut23;
+	    edif_cellref_t muxf5;
+
+	    lut01 = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
+	    edif_cellref_pstring(lut01, "INIT", "CA");
+
+	    lut23 = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
+	    edif_cellref_pstring(lut23, "INIT", "CA");
+
+	    muxf5 = edif_cellref_create(edf, xilinx_cell_muxf5(xlib));
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 0, idx));
+	    edif_add_to_joint(jnt, lut01, LUT_I0);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 1, idx));
+	    edif_add_to_joint(jnt, lut01, LUT_I1);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 2, idx));
+	    edif_add_to_joint(jnt, lut23, LUT_I0);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, 3, idx));
+	    edif_add_to_joint(jnt, lut23, LUT_I1);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net, 0));
+	    edif_add_to_joint(jnt, lut01, LUT_I2);
+	    edif_add_to_joint(jnt, lut23, LUT_I2);
+
+	    jnt = edif_joint_create(edf);
+	    edif_add_to_joint(jnt, muxf5, MUXF_I0);
+	    edif_add_to_joint(jnt, lut01, LUT_O);
+
+	    jnt = edif_joint_create(edf);
+	    edif_add_to_joint(jnt, muxf5, MUXF_I1);
+	    edif_add_to_joint(jnt, lut23, LUT_O);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
+	    edif_add_to_joint(jnt, muxf5, MUXF_O);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net, 1));
+	    edif_add_to_joint(jnt, muxf5, MUXF_S);
+      }
+}
+
+void virtex_mux(ivl_lpm_t net)
+{
+
+      switch (ivl_lpm_selects(net)) {
+
+	  case 2:
+	    virtex_mux4(net);
+	    break;
+
+	  default:
+	    xilinx_mux(net);
+	    break;
+      }
+}
+
 /*
  * This function generates ADD/SUB devices for Virtex devices,
  * based on the documented implementations of ADD8/ADD16, etc., from
@@ -750,7 +821,7 @@ const struct device_s d_virtex_edif = {
       virtex_eq,
       virtex_eq,
       virtex_ge,
-      xilinx_mux,
+      virtex_mux,
       virtex_add,
       virtex_add,
       xilinx_shiftl,
@@ -760,6 +831,9 @@ const struct device_s d_virtex_edif = {
 
 /*
  * $Log: d-virtex.c,v $
+ * Revision 1.31  2003/07/04 00:10:09  steve
+ *  Generate MUXF5 based 4-input N-wide muxes.
+ *
  * Revision 1.30  2003/07/02 03:02:15  steve
  *  More xilinx common code.
  *
diff --git a/tgt-fpga/d-virtex2.c b/tgt-fpga/d-virtex2.c
index 7458ef8bb..6d36310c5 100644
--- a/tgt-fpga/d-virtex2.c
+++ b/tgt-fpga/d-virtex2.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: d-virtex2.c,v 1.17 2003/07/02 03:02:15 steve Exp $"
+#ident "$Id: d-virtex2.c,v 1.18 2003/07/04 00:10:09 steve Exp $"
 #endif
 
 # include  "device.h"
@@ -84,7 +84,7 @@ const struct device_s d_virtex2_edif = {
       virtex_eq,
       virtex_eq,
       virtex_ge,
-      xilinx_mux,
+      virtex_mux,
       virtex_add,
       virtex_add,
       xilinx_shiftl, /* show_shiftl */
@@ -94,6 +94,9 @@ const struct device_s d_virtex2_edif = {
 
 /*
  * $Log: d-virtex2.c,v $
+ * Revision 1.18  2003/07/04 00:10:09  steve
+ *  Generate MUXF5 based 4-input N-wide muxes.
+ *
  * Revision 1.17  2003/07/02 03:02:15  steve
  *  More xilinx common code.
  *
diff --git a/tgt-fpga/xilinx.c b/tgt-fpga/xilinx.c
index 58553adb6..7a2e951ed 100644
--- a/tgt-fpga/xilinx.c
+++ b/tgt-fpga/xilinx.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: xilinx.c,v 1.7 2003/07/03 17:46:33 steve Exp $"
+#ident "$Id: xilinx.c,v 1.8 2003/07/04 00:10:09 steve Exp $"
 #endif
 
 # include  "edif.h"
@@ -99,6 +99,32 @@ edif_cell_t xilinx_cell_inv(edif_xlibrary_t xlib)
       return cell;
 }
 
+edif_cell_t xilinx_cell_muxf5(edif_xlibrary_t xlib)
+{
+      static edif_cell_t cell = 0;
+      if (cell) return cell;
+
+      cell = edif_xcell_create(xlib, "MUXF5", 4);
+      edif_cell_portconfig(cell, MUXF_O,  "O",  IVL_SIP_OUTPUT);
+      edif_cell_portconfig(cell, MUXF_I0, "I0", IVL_SIP_INPUT);
+      edif_cell_portconfig(cell, MUXF_I1, "I1", IVL_SIP_INPUT);
+      edif_cell_portconfig(cell, MUXF_S,  "S",  IVL_SIP_INPUT);
+      return cell;
+}
+
+edif_cell_t xilinx_cell_muxf6(edif_xlibrary_t xlib)
+{
+      static edif_cell_t cell = 0;
+      if (cell) return cell;
+
+      cell = edif_xcell_create(xlib, "MUXF6", 4);
+      edif_cell_portconfig(cell, MUXF_O,  "O",  IVL_SIP_OUTPUT);
+      edif_cell_portconfig(cell, MUXF_I0, "I0", IVL_SIP_INPUT);
+      edif_cell_portconfig(cell, MUXF_I1, "I1", IVL_SIP_INPUT);
+      edif_cell_portconfig(cell, MUXF_S,  "S",  IVL_SIP_INPUT);
+      return cell;
+}
+
 edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib)
 {
       static edif_cell_t cell = 0;
@@ -899,6 +925,9 @@ void xilinx_shiftl(ivl_lpm_t net)
 
 /*
  * $Log: xilinx.c,v $
+ * Revision 1.8  2003/07/04 00:10:09  steve
+ *  Generate MUXF5 based 4-input N-wide muxes.
+ *
  * Revision 1.7  2003/07/03 17:46:33  steve
  *  IOPAD support.
  *
diff --git a/tgt-fpga/xilinx.h b/tgt-fpga/xilinx.h
index aca52aa81..81a9def36 100644
--- a/tgt-fpga/xilinx.h
+++ b/tgt-fpga/xilinx.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: xilinx.h,v 1.6 2003/07/02 03:02:15 steve Exp $"
+#ident "$Id: xilinx.h,v 1.7 2003/07/04 00:10:09 steve Exp $"
 #endif
 
 /*
@@ -96,12 +96,23 @@ extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
 #define XORCY_CI 1
 #define XORCY_LI 2
 
+/* === Virtex/Virtex2 MUX devices */
+extern edif_cell_t xilinx_cell_muxf5(edif_xlibrary_t xlib);
+extern edif_cell_t xilinx_cell_muxf6(edif_xlibrary_t xlib);
+extern edif_cell_t xilinx_cell_muxf7(edif_xlibrary_t xlib);
+extern edif_cell_t xilinx_cell_muxf8(edif_xlibrary_t xlib);
+#define MUXF_O  0
+#define MUXF_I0 1
+#define MUXF_I1 2
+#define MUXF_S  3
+
 /* === Inheritable Methods === */
 
 extern void virtex_logic(ivl_net_logic_t net);
 extern void virtex_generic_dff(ivl_lpm_t net);
 extern void virtex_eq(ivl_lpm_t net);
 extern void virtex_ge(ivl_lpm_t net);
+extern void virtex_mux(ivl_lpm_t net);
 extern void virtex_add(ivl_lpm_t net);
 
 extern void xilinx_common_header(ivl_design_t des);
@@ -115,6 +126,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
 
 /*
  * $Log: xilinx.h,v $
+ * Revision 1.7  2003/07/04 00:10:09  steve
+ *  Generate MUXF5 based 4-input N-wide muxes.
+ *
  * Revision 1.6  2003/07/02 03:02:15  steve
  *  More xilinx common code.
  *